SN54LV273, SN74LV273

OCTAL DTYPE FLIPFLOPS

WITH CLEAR

SCLS195B − FEBRUARY 1993 − REVISED APRIL 1996

5

POST OFFICE BOX 655303

POST OFFICE BOX 1443

(unless otherwise noted) (see Figure 1)

FROM

TO

SN54LV273

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V ± 0.5 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

UNIT

fmax

60

100

50

80

40

MHz

tpd

CLK

Q

11

16

16

22

26

ns

tPHL

CLR

Q

13

22

14

24

30

ns

(unless otherwise noted) (see Figure 1)

FROM

TO

SN74LV273

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V ± 0.5 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

UNIT

fmax

60

100

50

80

40

MHz

tpd

CLK

Q

11

16

16

22

26

ns

tPHL

CLR

Q

13

22

14

24

30

ns

PARAMETER

TEST CONDITIONS

VCC

TYP

UNIT

Cpd

Power dissipation capacitance per flip-flop

CL = 50 pF,

f = 10 MHz

3.3 V

32

pF

Cpd

Power dissipation capacitance per flip-flop

CL = 50 pF,

f = 10 MHz

5 V

41

pF

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.