SN74HC74-Q1

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP

WITH CLEAR AND PRESET

SCLS577A − MARCH 2004 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

CC

description/ordering information

The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When

PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred

to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and

is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed

without affecting the levels at the outputs.

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40

°C to 125°C

SOIC − D

Reel of 2500

SN74HC74QDRQ1

HC74Q

−40

°C to 125°C

TSSOP − PW

Reel of 2000

SN74HC74QPWRQ1

HC74Q

this document, or see the TI web site at http://www.ti.com.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

persist when PRE or CLR returns to its inactive

(high) level.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

1Q

GND

2CLR

2D

2CLK

2PRE

2Q

2Q

D OR PW PACKAGE

(TOP VIEW)

Copyright

 2008, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.