74LVCH16952ADGVRG4 datasheet(5/14 Pages) TI1

部品番号	74LVCH16952ADGVRG4

部品情報	16-BIT REGISTERED TRANSCEIVER

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Electrical Characteristics

Timing Requirements

SN74LVCH16952A

16-BIT REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS320L – NOVEMBER 1993 – REVISED MARCH 2005

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN TYP(1)

MAX

UNIT

IOH = –100 µA

1.65 V to 3.6 V

VCC – 0.2

IOH = –4 mA

1.65 V

1.2

IOH = –8 mA

2.3 V

1.7

VOH

V

2.7 V

2.2

IOH = –12 mA

3 V

2.4

IOH = –24 mA

3 V

2.2

IOL = 100 µA

1.65 V to 3.6 V

0.2

IOL = 4 mA

1.65 V

0.45

VOL

IOL = 8 mA

2.3 V

0.7

V

IOL = 12 mA

2.7 V

0.4

IOL = 24 mA

3 V

0.55

II

Control inputs VI = 0 to 5.5 V

3.6 V

±5

µA

VI = 0.58 V

15

1.65 V

VI = 1.07 V

–15

VI = 0.7 V

45

2.3 V

II(hold)

A or B ports

VI = 1.7 V

–45

µA

VI = 0.8 V

75

3 V

VI = 2 V

–75

VI = 0 to 3.6 V(2)

3.6 V

±500

Ioff

VI or VO = 5.5 V

0

±10

µA

IOZ(3)

VO = 0 V or (VCC to 5.5 V)

3.6 V

±10

µA

VI = VCC or GND, IO = 0

20

ICC

3.6 V

µA

3.6 V

≤ V

I ≤ 5.5 V

(4), I

O = 0

20

∆I

CC

One input at VCC – 0.6 V, Other inputs at VCC or GND

2.7 V to 3.6 V

500

µA

Ci

Control inputs VI = VCC or GND

3.3 V

5

pF

Cio

A or B ports

VO = VCC or GND

3.3 V

8.5

pF

(1)

All typical values are at VCC = 3.3 V, TA = 25°C.

(2)

This is the bus-hold maximum dynamic current required to switch the input from one state to another.

(3)

For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI <VCC, and the

IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is

negligible.

(4)

This applies in the disabled state only.

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

VCC = 1.8 V

VCC = 2.5 V

VCC = 3.3 V

VCC = 2.7 V

± 0.15 V

± 0.2 V

± 0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

130

150

MHz

tw

Pulse duration, CLK high or low

5

3.3

ns

Data before CLK

↑

5.8

3.4

2.8

tsu

Setup time

ns

CE before CLK

↑

1.4

1.3

1.8

1.4

Data after CLK

↑

0

0.5

th

Hold time

ns

CE after CLK

↑

1.1

1.6

1.1

1.9

5

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