OE1

OE2

To Seven Other Channels

A1

Y1

SN74LV541A

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SCLS410J – APRIL 1998 – REVISED DECEMBER 2014

9 Detailed Description

9.1 Overview

The SN74LV541A device is ideal for driving bus lines or buffer memory address registers. It features inputs and

outputs on opposite sides of the package to facilitate printed circuit board layout.

The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or

OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide non-inverted

data when they are not in the high-impedance state.

pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

9.2 Functional Block Diagram

Figure 4. Logic Diagram (Positive Logic)

9.3 Feature Description

•

Wide operating voltage range

–

Operates from 2 V to 5.5 V

•

Allows down-voltage translation

–

Inputs accept voltages to 5.5 V

•

–

9.4 Device Functional Modes

Table 2. Function Table

(Each Buffer or Driver)

INPUTS

OUTPUT

Y

OE1

OE2

A

L

L

L

L

L

L

H

H

H

X

X

Z

X

H

X

Z

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