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SN74V245-EP データシート(PDF) 3 Page - Texas Instruments |
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SN74V245-EP データシート(HTML) 3 Page - Texas Instruments |
3 / 42 page PAG PACKAGE (TOP VIEW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SN74V245-EP www.ti.com SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. D0–D17 1-16, 63, 64 I Data inputs. Data inputs for an 18-bit bus. Memory-empty/valid-data-available flag. In the standard mode, the EF function is selected. EF/OR 54 O EF indicates whether the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether there is valid data available at the outputs. Memory-full/space-available flag. In the standard mode, the FF function is selected. FF FF/IR 25 O indicates whether the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether there is space available for writing to the FIFO memory. Mode selection. In the single-device or width-expansion configuration, FL, together with WXI and RXI, determines if the mode is standard mode or first-word fall-through (FWFT) mode, FL 18 I as well as whether the PAE/PAF flags are synchronous or asynchronous (see Table 5). In the daisy-chain depth-expansion configuration, FL is grounded on the first device (first-load device) and set to high for all other devices in the daisy chain. 30, 35, 40, 46, 51, GND Ground 55, 62 Read/write control. When LD is low, data on the inputs D0–D11 is written to the offset and depth registers on the low-to-high transition of the WCLK, when WEN is low. When LD is LD 59 I low, data on the outputs Q0–Q11 is read from the offset and depth registers on the low-to- high transition of RCLK when REN is low. Output enable. When OE is low, the data output bus is active. If OE is high, the output data OE 58 I bus is in the high-impedance state. Programable almost-empty flag. When PAE is low, the FIFO is almost empty, based on the PAE 17 O offset programmed into the FIFO. The default offset at reset is 127 from empty. Programable almost-full flag. When PAF is low, the FIFO is almost full, based on the offset PAF 23 O programmed into the FIFO. The default offset at reset is 127 from full. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN74V245-EP |
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