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TL16C2552 データシート(PDF) 7 Page - Texas Instruments |
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TL16C2552 データシート(HTML) 7 Page - Texas Instruments |
7 / 34 page www.ti.com Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Modem Status Register Line Control Register Transmitter FIFO Interrupt Enable Register Interrupt Identification Register FIFO Control Register Select and Control Logic Interrupt Control Logic S e l e c t Data Bus Buffer RXA, B TXA, B CTSA, B DTRA, B DSRA, b CDA,B RIA, B INTA, B 40, 28 37, 27 41, 29 42, 30 43, 31 34, 17 38, 26 39, 25 A0 10 D(7 −0) 9−2 Internal Data Bus 14 15 18 16 13 21 24 20 11 1 35 A1 A2 CS CHSEL XTAL2 RESET IOR IOW XTAL1 TXRDYA MFA S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Modem Control Logic 8 33, 44 12, 22 VCC GND Power Supply RTSA, B 36, 23 Autoflow Control (AFE) 8 8 8 8 8 8 8 32 19 TXRDYB MFB Crystal OSC Buffer TL16C2552 SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 A. Pin numbers shown are for 44-pin PLCC FN package. Figure 5. Functional Block Diagram 7 Submit Documentation Feedback |
同様の部品番号 - TL16C2552_16 |
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同様の説明 - TL16C2552_16 |
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