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CS8414 データシート(PDF) 9 Page - List of Unclassifed Manufacturers |
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CS8414 データシート(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 38 page CS8413 CS8414 DS240F1 9 Status and IEnable Registers The status and interrupt enable registers occupy the same address space. The IER/SR bit in control reg- ister 1 selects whether the status registers (IER/SR = 0) or the IEnable registers (IER/SR = 1) occupy addresses 0 and 1. Upon power-up, the con- trol and IEnable registers contain all zeros; there- fore, the status registers are visible and all interrupts are disabled. The IER/SR bit must be set to make the IEnable registers visible. Status register 1 (SR1), shown in Figure 6, reports all the conditions that can generate a low pulse four SCLK cycles wide on the interrupt pin (INT). The three least significant bits, FLAG2-FLAG0, are used to monitor the ram buffer. These bits continu- ally change and indicate the position of the buffer pointer which points to the buffer memory location currently being written. Each flag has a corre- sponding interrupt enable bit in IEnable register 1 which, when set, allows a transition on the flag to generate a pulse on the interrupt pin. FLAG0 and FLAG1 cause interrupts on both edges whereas FLAG2 causes an interrupt on the rising edge only. Further information, including timing, on the flags can be found in the Buffer Memory section. The next five bits; ERF, SLIP, CCHG, CRCE/CRC1, and CSDIF/CRC2, are latches which are set when their corresponding conditions occur, and are reset when SR1 is read. Interrupt RXP RXN VD+ DGND VA+ FILT AGND MCK FSYNC SCK SDATA INT ERF CS RD/WR A4/ FCK A0- A3 D0- D7 9 10 7 8 22 20 21 19 11 12 26 14 25 24 23 13 48 Clock & Data Recovery Bi-phase Decoder De-Multiplexor crc check Audio Serial Port Control Registers 2 X 8 Buffer Memory 28 X 8 IEnable & Status 4 X 8 aux user C.S. slipped parity validity crc coding no lock Frequency Comparator Figure 4. CS8413 Block Diagram |
同様の部品番号 - CS8414 |
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同様の説明 - CS8414 |
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