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TLC2552ID データシート(PDF) 4 Page - Texas Instruments |
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TLC2552ID データシート(HTML) 4 Page - Texas Instruments |
4 / 28 page TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS276D – MARCH 2000 – REVISED MAY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) GND/AIN(–) ADC Code AIN Charge Redistribution DAC Control Logic _ + Figure 1. Simplified SAR Circuit serial interface OUTPUT DATA FORMAT MSB LSB D15–D4 D3–D0 Conversion result (OD11–OD0) Don’t care The output data format is binary (unipolar straight binary). binary Zero-scale code = 000h, Vcode = GND Full-scale code = FFFh, Vcode = VREF – 1 LSB pseudo-differential inputs The TLC2555 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a maximum input ripple of ±0.2 V. This is normally used for ground noise rejection. control and timing start of the cycle Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever CS (pin 1) is high to assure proper operation. TLC2551 D Control via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB may be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI interface may be programmed for CPOL = 0 (serial clock referenced to ground) and CPHA = 1 (data is valid on the falling edge of serial clock). At least one falling edge transition on SCLK is needed whenever CS is brought high. D Control via FS—The MSB is presented after the rising edge of FS. The falling edge of FS starts the cycle. The MSB may be read on the first falling edge of SCLK after FS is low. This is the typical configuration when the ADC is the only device on the DSP serial port. |
同様の部品番号 - TLC2552ID |
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同様の説明 - TLC2552ID |
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