TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

10

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = – 2 mA

4

V

VOL

Low-level output voltage

IOL = 2 mA

0.5

V

VIT

Input threshold voltage

SELECT1, SELECT2,

VCOINHIBIT1, VCOINHIBIT2

1.5

2.5

3.5

V

II

Input current

SELECT1, SELECT2,

VCOINHIBIT1, VCOINHIBIT2

VI = VDD or GND

±1

µA

Zi(VCOIN)

Input impedance

VCOIN1, VCOIN2

VCOIN = 1/2 VDD

10

M

Ω

IDD(INH)

VCO supply current (inhibit) (each chip)

See Note 4

0.01

1

µA

IDD(VCO)

VCO supply current (each chip)

See Note 10

15

35

mA

NOTES: 4.

The current into VCO VDD and LOGIC VDD when VCOINHIBIT = VDD, and the PFD is inhibited.

10. The current into VCO VDD and LOGIC VDD when VCOIN = 1/2 VDD, RBIAS = 2.2 kΩ, VCOINHIBIT = GND, and the PFD is inhibited.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = 2 mA

4.5

V

VOL

Low-level output voltage

IOL = 2 mA

0.2

V

IOZ

High-impedance output current

PFD INHIBIT1, PFD INHIBIT2 = high,

VO = VDD or GND

±1

µA

VIH

High-level input voltage

FIN–A1, FIN–B1,

FIN–A2, FIN–B2

4.5

V

VIL

Low-level input voltage

FIN–A1, FIN–B1,

FIN–A2, FIN–B2

1

V

VIT

Input threshold voltage

PFD INHIBIT2,

PFD INHIBIT1

1.5

2.5

3.5

V

Ci

Input capacitance

FIN–A1, FIN–B1,

FIN–A2, FIN–B2

5

pF

Zi

Input impedance

FIN–A1, FIN–B1,

FIN–A2, FIN–B2

10

M

Ω

IDD(Z)

High-impedance state PFD supply current

See Note 6

0.1

1

µA

IDD(PFD)

PFD supply current (each chip)

See Note 11

0.15

3

mA

NOTES:

6. The current into LOGIC VDD, when FIN–A and FIN–B = GND, PFD INHIBIT= VDD, no load, and VCO OUT is inhibited.

11. The current into LOGIC VDD when FIN–A and FIN–B = 1 MHz with VI(PP) = 5-V rectangular wave, PFD INHIBIT = GND, no load,

and

VCO OUT is inhibited.