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TDA6650 データシート(PDF) 10 Page - NXP Semiconductors |
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TDA6650 データシート(HTML) 10 Page - NXP Semiconductors |
10 / 55 page 2004 Mar 22 10 Philips Semiconductors Product specification 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) TDA6650TT; TDA6651TT Table 4 Description of write data format bits 8.1.1 I2C-BUS ADDRESS SELECTION The device address contains programmable address bits MA1 and MA0, which offer the possibility of having up to four MOPLL ICs in one system. Table 5 gives the relationship between the voltage applied to the AS input and the MA1 and MA0 bits. Table 5 Address selection BIT DESCRIPTION A acknowledge MA1 and MA0 programmable address bits; see Table 5 R/W logic 0 for write mode N14 to N0 programmable LO frequency; N = N14 × 214 + N13 × 213 + N12 × 212 + ... + N1 × 21 +N0 T/A test/AGC bit T/A = 0: the next six bits sent are AGC settings T/A = 1: the next six bits sent are test and reference divider ratio settings T2, T1 and T0 test bits; see Table 6 R2, R1, and R0 reference divider ratio and programmable frequency step; see Table 7 ATC AGC current setting and time constant; capacitor on pin AGC = 150 nF ATC = 0: AGC current = 220 nA; AGC time constant = 2 s ATC = 1: AGC current = 9 µA; AGC time constant = 50 ms AL2, AL1 and AL0 AGC take-over point bits; see Table 8 CP2, CP1 and CP0 charge pump current; see Table 9 BS5, BS4, BS3, BS2 and BS1 PMOS ports control bits BSn = 0: corresponding port is off, high-impedance state (status at Power-on reset) BSn = 1: corresponding port is on; VO =VCC − VDS(sat) VOLTAGE APPLIED TO PIN AS MA1 MA0 0 V to 0.1VCC 00 0.2VCC to 0.3VCC or open-circuit 0 1 0.4VCC to 0.6VCC 10 0.9VCC to VCC 11 |
同様の部品番号 - TDA6650 |
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同様の説明 - TDA6650 |
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