5

UC1826

UC2826

UC3826

ENBL: The active low input with a 2.5V threshold en-

ables the output to switch. SEQ and RUN are driven low

when ENBL is above its 2.5V threshold.

GND: The signal ground used for the voltage sense am-

plifier, current error amplifier, current error amplifier, volt-

age reference, 2X amplifier, and share amplifier. The

output sink transistor is wired directly to this pin.

KILL: The active low input with a 3.0V threshold stops

the output from switching. Once this function is activated

RUN must be cycled low by driving KILL above 3.0V and

either resetting the power to the chip (VCC) or resetting

the ENBL signal.

ILIM: A voltage on this pin programs the voltage error

amplifier’s Voh clamp. The voltage error amplifier output

represents the average output current. The Voh clamp

consequently limits the output current. If ILIM is tied to

VREF, it defaults to 3.0V. A voltage less than 3.0V con-

nected to ILIM clamps the voltage error amplifier at this

voltage and consequently limits the maximum output cur-

rent.

OSC:The oscillator ramp (not to be confused with PWM

charge current. The oscillator charges from 1.2V to 3.4V

until the output transitions low. At this time an open col-

pacitor through RDEAD.

()

1

1

Frequency

TT

CHARGE

DISCHARGE

≈

+

()

2

Maximum Duty Cycle

T

TT

CHARGE

CHARGE

DISCHARGE

≈

+

mately 40pF to account for parasitic capacitance.

OUT: The output of the PWM driver. It has an upper

clamp of 8.5V. The peak current sink and source are

250mA. All UVLO, SEQ, ENBL, and KILL logic either en-

able or disable the output driver.

PWRSEN: This pin is the input to the PWROK compara-

tor.

PWROK: The output pin from the PWROK comparator. It

has a 300 A current source output when driven high.

RAMP: An open collector that can sink 20mA to dis-

charge the oscillator capacitor. An RC is tied between

VCC and GND to accomplish feedforward. The PWM

output drives this pin. When the output is high, the tran-

sistor is off enabling the charging of the RAMP capacitor.

When the output transitions low, the transistor is turned

on discharging the RAMP capacitor. The voltage at

RAMP rises from 0.2V to near 4V at maximum duty cy-

cle. Although this is an exponential ramp at high VCC

voltage the ramp appears linear.

RDEAD: The pin that programs the maximum duty cycle

by connecting a resistor between it and OSC. The maxi-

mum duty cycle is decreased by increasing this resistor

value which increases the discharge time. The dead time,

the time when the output is low, is 2

capacitance should be increased by approximately 40pF

to account for parasitic capacitance.

RUN: This is an open collector logic output that signifies

when the chip is operational. RUN is pulled high to VREF

through an external resistor when VCC is greater than

8.4V, VREF is greater than 4.65V, SEQ is greater than

2.5V, and KILL lower than 3.0V. RUN connected to the

VA+ pin and to a capacitor to ground adds an RC rise

time on the VA+ pin initiating a soft start.

SEQ: The sequence pin allows the sequencing of startup

for multiple units. A resistor between VREF and SEQ and

a capacitor between SEQ and GND create a unique RC

rise time for each unit which sequences the output

startup.

SHARE:The nearly DC voltage representing the average

output current. This pin is wired directly to all SHARE

pins and is the load share bus.

VA–, VA+: The inverting and non-inverting inputs to the

voltage error amplifier.

VAO: The output of the voltage error amplifier. Its Voh is

clamped with the ILIM pin.

VCC: The input voltage to the chip. The chip is opera-

tional between 8.4V and 20V.

VEE: The negative supply voltage to the chip which pow-

ers the lower voltage rail for all amplifiers. The chip is op-

erational if VEE is connected to GND or if GND is

floating. When voltage is applied externally to VEE, GND

becomes a virtual ground because of an internal diode

between VEE and GND. The GND current flows through

the forward biased diode and out VEE. GND is always

the signal ground from which the voltage reference and

all amplifier inputs are referenced.

VREF: The reference voltage equal to 5.0V.

PIN DESCRIPTIONS (cont.)