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MC100EPT20D データシート(PDF) 1 Page - ON Semiconductor |
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MC100EPT20D データシート(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2004 September, 2004 − Rev. 7 1 Publication Order Number: MC10EPT20/D MC10EPT20, MC100EPT20 3.3VLVTTL/LVCMOS to Differential LVPECL Translator The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the EPT20 makes it ideal for those applications where space, performance, and low power are at a premium. The 100 Series contains temperature compensation. • 390 ps Typical Propagation Delay • Maximum Input Clock Frequency > 1 GHz Typical • Operating Range V CC = 3.0 V to 3.6 V with GND = 0 V • PNP TTL Input for Minimal Loading • Q Output will Default HIGH with Input Open • Pb−Free Packages are Available L = Wafer Lot Y = Year W = Work Week H = MC10 K = MC100 A = Assembly Location MARKING DIAGRAMS* ALYW HA20 ALYW KA20 SO−8 D SUFFIX CASE 751 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 1 8 *For additional marking information, refer to Application Note AND8002/D. 1 8 HPT20 ALYW 1 8 KPT20 ALYW 1 8 http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ORDERING INFORMATION |
同様の部品番号 - MC100EPT20D |
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同様の説明 - MC100EPT20D |
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