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TPIC6A596 データシート(PDF) 1 Page - Texas Instruments |
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TPIC6A596 データシート(HTML) 1 Page - Texas Instruments |
1 / 16 page TPIC6A596 POWER LOGIC 8BIT SHIFT REGISTER SLIS094A − MARCH 2000 − REVISED MAY 2005 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Low rDS(on) ...1 Ω Typ D Output Short-Circuit Protection D Avalanche Energy . . . 75 mJ D Eight 350-mA DMOS Outputs D 50-V Switching Capability D Enhanced Cascading for Multiple Stages D All Registers Cleared With Single Input D Low Power Consumption description The TPIC6A596 is a monolithic, high-voltage, high-current power logic 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium- current or high-voltage loads. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit, D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift- register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift- register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability. Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits. The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount (DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of −40 °C to 125°C. Copyright 2000 − 2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DRAIN2 DRAIN3 SRCLR G PGND PGND RCK SRCK DRAIN4 DRAIN5 DRAIN1 DRAN0 SER IN VCC PGND PGND LGND SER OUT DRAIN7 DRAIN6 NE PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DRAIN2 DRAIN3 SRCLR G PGND PGND PGND PGND RCK SRCK DRAIN4 DRAIN5 DRAIN1 DRAIN0 SER IN VCC PGND PGND PGND PGND LGND SER OUT DRAIN7 DRAIN6 DW PACKAGE (TOP VIEW) |
同様の部品番号 - TPIC6A596_15 |
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同様の説明 - TPIC6A596_15 |
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