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TPIC6596 データシート(PDF) 5 Page - Texas Instruments |
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TPIC6596 データシート(HTML) 5 Page - Texas Instruments |
5 / 16 page TPIC6596 POWER LOGIC 8BIT SHIFT REGISTER SLIS096A − APRIL 2000 − REVISED MAY 2005 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output from G 650 ns tPHL Propagation delay time, high-to-low-level output from G CL = 30 pF, ID = 250 mA, 200 ns tr Rise time, drain output CL = 30 pF, ID = 250 mA, See Figures 1, 2, and 11 230 ns tf Fall time, drain output See Figures 1, 2, and 11 170 ns tpd Propagation delay time, SRCK ↓ to SER OUT CL = 30 pF, ID = 250 mA, See Figure 2 50 ns f(SRCK) Serial clock frequency CL = 30 pF, ID = 250 mA, See Note 8 5 MHz ta Reverse-recovery-current rise time IF = 250 mA, di/dt = 20 A/ µs, 100 ns trr Reverse-recovery time IF = 250 mA, di/dt = 20 A/ µs, See Notes 5 and 6 and Figure 3 300 ns NOTES: 5. Technique should limit TJ − TC to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows SRCK → SER OUT propagation delay and setup time plus some timing margin. thermal resistance PARAMETER TEST CONDITIONS MIN MAX UNIT R JA Thermal resistance, junction-to-ambient DW package All 8 outputs with equal power 111 °C/W RθJA Thermal resistance, junction-to-ambient N package All 8 outputs with equal power 108 °C/W PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT 5 V VCC DRAIN LGND SRCLR SER IN RL = 95 Ω CL = 30 pF (see Note B) VOLTAGE WAVEFORMS G Output SRCK RCK Word Generator (see Note A) 7654 3210 5 V SRCK 5 V G 5 V SER IN RCK SRCLR 5 V 5 V DUT PGND 24 V DRAIN1 24 V 0 V 0 V 0 V 0.5 V 0 V 19 1, 10, 11, 20 8 13 3 12 9 0 V 4 −7, 14 −17 ID 2 Figure 1. Resistive Load Operation |
同様の部品番号 - TPIC6596 |
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同様の説明 - TPIC6596 |
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