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CS8406-DS データシート(PDF) 9 Page - Cirrus Logic |
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CS8406-DS データシート(HTML) 9 Page - Cirrus Logic |
9 / 43 page CS8406 DS580F1 9 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes: 9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. 10. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns. 11. Data must be held for sufficient time to bridge the transition time of CCLK. 12. For fsck < 1 MHz. Parameter Symbol Min Typ Max Units CCLK Clock Frequency (Note 9) fsck 0- 6.0 MHz CS High Time Between Transmissions tcsh 1.0 - - µs CS Falling to CCLK Edge tcss 20 - - ns CCLK Low Time tscl 66 - - ns CCLK High Time (Note 10) tsch MAX ((1/256 FS + 8), 66) ns CDIN to CCLK Rising Setup Time tdsu 40 - - ns CCLK Rising to DATA Hold Time (Note 11) tdh 15 - - ns CCLK Falling to CDOUT Stable tpd - - 50 ns Rise Time of CDOUT tr1 - - 25 ns Fall Time of CDOUT tf1 - - 25 ns Rise Time of CCLK and CDIN (Note 12) tr2 - - 100 ns Fall Time of CCLK and CDIN (Note 12) tf2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 3. SPI Mode timing |
同様の部品番号 - CS8406-DS |
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同様の説明 - CS8406-DS |
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