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Si5380-D-EVB データシート(PDF) 9 Page - Silicon Laboratories

部品番号 Si5380-D-EVB
部品情報  Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
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メーカー  SILABS [Silicon Laboratories]
ホームページ  http://www.silabs.com
Logo SILABS - Silicon Laboratories

Si5380-D-EVB データシート(HTML) 9 Page - Silicon Laboratories

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3.2 External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low phase noise reference clock
for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in the figure
below. The Si5380 includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit
of reduced noise coupling from external sources. Refer to the Table 5.12 Crystal Specifications on page 34 for crystal specifications.
A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The Si5380 includes
built-in XTAL load capacitors (CL) of 8 pF, which are switched out of the circuit when using an external XO. The Si5380 Reference
Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To ach-
ieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g., XO) may
be used in lieu of the crystal, but it may result in higher output jitter. See the Si5380 Reference Manual for more information. Selection
between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled
in this mode. It is important to note that when using the REFCLK option the phase noise of the outputs is directly affected by the phase
noise of the external XO reference. Refer to the Table 5.3 Input Clock Specifications on page 24 for REFCLK requirements when
using the REFCLK mode.
Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load condi-
tions, and aging.
OSC
XB
XA
54MHz
XTAL
2xCL
2xCL
Crystal Resonator Connection
OSC
XB
XA
54MHz
XO
100
Differential XO Connection
OSC
XB
XA
54MHz
XO
Single-Ended XO Connection
2xCL
2xCL
2xCL
Si5380
Si5380
Si5380
2xCL
÷PREF
÷PREF
÷PREF
Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options
3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN)
Four clock inputs are available to synchronize the DSPLL. The inputs are compatible with both single-ended and differential signals.
Input selection can be manual (pin or register controlled) or automatic with definable priorities.
Si5380 Rev D Data Sheet
Functional Description
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 8


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