PRINTED CIRCUIT BOARD LAYOUT, COMPONENT

VALUES SELECTION, AND EVALUATION BOARDS

Generally, a good high-frequency layout will keep power

supply and ground traces away from the inverting input and

output pins. Parasitic capacitances on these nodes to

ground will cause frequency response peaking and possible

circuit oscillations (see Application Note OA-15 for more

information).

Another important parameter, is the component values se-

lection. Choosing large valued external resistors, will effect

the closed loop behavior of the stage because of the inter-

action of these resistors with parasitic capacitances. These

capacitors could be inherent to the device or a by-product of

the board layout and component placement. Either way,

keeping the resistor values lower, will diminish this interac-

tion. On the other hand, choosing very low value resistors

could load down nodes and will contribute to higher overall

power dissipation.

National Semiconductor suggests the following evaluation

boards as a guide for high frequency layout and as an aid in

device testing and characterization:

Device

Package

Evaluation

Board PN

LMV116

SOT23-5

CLC730068

LMV118

SOT23-6

CLC730116

These free evaluation boards are shipped when a device

sample request is placed with National Semiconductor.

www.national.com

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