データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

GS82582S18 データシート(PDF) 5 Page - GSI Technology

部品番号 GS82582S18
部品情報  288Mb SigmaSIOTM DDR-II Burst of 2 SRAM
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS82582S18 データシート(HTML) 5 Page - GSI Technology

  GS82582S18 Datasheet HTML 1Page - GSI Technology GS82582S18 Datasheet HTML 2Page - GSI Technology GS82582S18 Datasheet HTML 3Page - GSI Technology GS82582S18 Datasheet HTML 4Page - GSI Technology GS82582S18 Datasheet HTML 5Page - GSI Technology GS82582S18 Datasheet HTML 6Page - GSI Technology GS82582S18 Datasheet HTML 7Page - GSI Technology GS82582S18 Datasheet HTML 8Page - GSI Technology GS82582S18 Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 31 page
background image
GS82582S18/36GE-400/375/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2016
5/31
© 2012, GSI Technology
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at
the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write
addresses like SigmaCIO SRAMs, but in a separate I/O configuration.
Like a SigmaQuad SRAM, a SigmaSIO DDR-II SRAM can execute an alternating sequence of reads and writes. However, doing
so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would
keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read
commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts
the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice
the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device.
SigmaDDR (CIO) SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the
SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of
burst traffic between two electrically independent busses is desired.
Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaDDR, and SigmaSIO—supports similar address rates because
random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are
based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how
the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to
the application at hand.
Burst of 2 SigmaSIO DDR-II SRAM DDR Read
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on
the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is
clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data
chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.
Burst of 2 SigmaSIO DDR-II SRAM DDR Write
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the
R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.


同様の部品番号 - GS82582S18

メーカー部品番号データシート部品情報
logo
GSI Technology
GS82582D18GE-333I GSI-GS82582D18GE-333I Datasheet
529Kb / 30P
   288Mb SigmaQuad-IITM Burst of 4 SRAM
GS82582D19GE-333 GSI-GS82582D19GE-333 Datasheet
443Kb / 26P
   288Mb SigmaQuad-IITM Burst of 4 SRAM
GS82582D19GE-375 GSI-GS82582D19GE-375 Datasheet
443Kb / 26P
   288Mb SigmaQuad-IITM Burst of 4 SRAM
GS82582D19GE-375I GSI-GS82582D19GE-375I Datasheet
443Kb / 26P
   JEDEC-standard pinout and package
GS82582D19GE-400I GSI-GS82582D19GE-400I Datasheet
443Kb / 26P
   JEDEC-standard pinout and package
More results

同様の説明 - GS82582S18

メーカー部品番号データシート部品情報
logo
GSI Technology
GS8662S08 GSI-GS8662S08 Datasheet
1Mb / 35P
   72Mb SigmaSIOTM DDR -II Burst of 2 SRAM
GS81302S08 GSI-GS81302S08 Datasheet
1Mb / 35P
   144Mb SigmaSIOTM DDR -II Burst of 2 SRAM
GS82582Q20GE-500I GSI-GS82582Q20GE-500I Datasheet
436Kb / 25P
   288Mb SigmaQuad-II Burst of 2 SRAM
GS82582Q20GE-450I GSI-GS82582Q20GE-450I Datasheet
436Kb / 25P
   288Mb SigmaQuad-II Burst of 2 SRAM
GS82582Q19GE-400 GSI-GS82582Q19GE-400 Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582TT20 GSI-GS82582TT20 Datasheet
438Kb / 24P
   288Mb SigmaDDR-IITM Burst of 2 SRAM
GS82582Q37GE-300 GSI-GS82582Q37GE-300 Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582T20 GSI-GS82582T20 Datasheet
444Kb / 26P
   288Mb SigmaDDR-IITM Burst of 2 SRAM
GS82582QT19GE-400I GSI-GS82582QT19GE-400I Datasheet
325Kb / 26P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582Q19GE-400I GSI-GS82582Q19GE-400I Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com