AD7401BRW datasheet(3/10 Pages) AD

部品番号	AD7401BRW

部品情報	Isolated Sigma-Delta Modulator

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Preliminary Technical Data

AD7400/AD7401

AD7400—SPECIFICATIONS1

Table 1. (VDD1 = VDD2 = 4.5V to 5.5V, , VIN+ = -200mV to +200mV and VIN- = 0V; TA = TMIN to TMAX, fMCLK = 10MHz unless

otherwise noted.)

Parameter

B Version1,5

Units

Test Conditions/Comments

STATIC PERFORMANCE

When Tested with Sinc3 Filter4

Resolution

16

Bits min

Filter output trunctaed to 16 Bits

Integral Nonlinearity2

±4

LSB max

Differential Nonlinearity2

±0.9

LSB max

Guaranteed No Missed Codes to 15 bits

Offset Error2

±0.5

mV max

Bipolar Input Range

Offset Drift vs. Temperature2

5

2

µV/ C max

µV/ C typ

Offset Drift vs. VDD12

0.05

mV/V typ

Absolute Reference Voltage Tolerance

±1

%min/max

Reference Voltage Matching

±TBD

%min/max

VREF Drift vs. Temperature2

60

ppm/ C typ

VREF Drift vs. VDD12

0.2

% typ

ANALOG INPUT

Input Voltage Ranges6

±200

mV min/max

DC Leakage Current

±1

µA max

DYNAMIC SPECIFICATIONS

When Tested with Sinc3 Filter4

Signal to Noise + Distortion Ratio (SINAD) 2

70

76

dBmin

dB typ

VIN+ = 35Hz, 400mVpk-pk sine wave

Total Harmonic Distortion (THD)2

-80

dB typ

Peak Harmonic or Spurious Noise (SFDR)2

-70

dB typ

Effective number of bits

12

Bits

Isolation Transient Immunity

15

20

kV/µs min

kV/µs typ

Signal Delay

20

24

µs typ

µs max

Delay through filter varies with actual value of on-

board clock. Decimation by 2.

LOGIC INPUTS

Input High Voltage, VINH

2

V min

Input Low Voltage, VINL

0.8

V max

Input Current, IIN

±1

µA max

Input Capacitance, CIN3

10

pF max

LOGIC OUTPUTS

Output High Voltage, VOH

VDD2 – 0.1

V min

IO = -20 µA

Output Low Voltage, VOL

0.4

V max

IO = 20 µA

POWER REQUIREMENTS

VDD1

+4.5/+5.5

Vmin/Vmax

VDD2

+4.5/+5.5

Vmin/Vmax

+2.7/+3.3

Vmin/Vmax

IDD17

18.1

mA max

IDD27

1.96

mA max

VDD1 = 5V, Digital I/Ps = 0 V or VDD1

NOTES

1 Temperature ranges as follows: -40 C to +105 C

2 See Terminology section.

3 Sample tested @ 25 C to ensure compliance.

4 Filter as defined by Verilog Code.

5 All voltages are relative to their respective ground.

6 Beyond the full-scale input range the output is either all zeroes or all ones.

Specifications subject to change without notice.

Rev. PrH | Page 3 of 10

同様の部品番号 - AD7401BRW

メーカー	部品番号	データシート	部品情報
Analog Devices	AD7401	462Kb / 20P	Isolated Sigma-Delta Modulator REV. 0
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同様の説明 - AD7401BRW

メーカー	部品番号	データシート	部品情報
Analog Devices	AD7401	347Kb / 20P	Isolated Sigma-Delta Modulator REV. D
	AD7401A	551Kb / 20P	Isolated Sigma-Delta Modulator Rev. D
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	AD7401A	436Kb / 20P	Isolated Sigma-Delta Modulator REV. 0
	AD7400	444Kb / 20P	Isolated Sigma-Delta Modulator REV. A
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