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AD9235BRU-20 データシート(PDF) 3 Page - Analog Devices |
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AD9235BRU-20 データシート(HTML) 3 Page - Analog Devices |
3 / 32 page REV. B –3– AD9235 DIGITAL SPECIFICATIONS Test AD9235BRU-20 AD9235BRU-40 AD9235BRU/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA Low Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA Input Capacitance Full V 2 2 2 pF LOGIC OUTPUTS * DRVDD = 3.3 V High-Level Output Voltage Full IV 3.29 3.29 3.29 V (IOH = 50 µA) High-Level Output Voltage Full IV 3.25 3.25 3.25 V (IOH = 0.5 mA) Low-Level Output Voltage Full IV 0.2 0.2 0.2 V (IOL = 1.6 mA) Low-Level Output Voltage Full IV 0.05 0.05 0.05 V (IOL = 50 µA) DRVDD = 2.5 V High-Level Output Voltage Full IV 2.49 2.49 2.49 V (IOH = 50 µA) High-Level Output Voltage Full IV 2.45 2.45 2.45 V (IOH = 0.5 mA) Low-Level Output Voltage Full IV 0.2 0.2 0.2 V (IOL = 1.6 mA) Low-Level Output Voltage Full IV 0.05 0.05 0.05 V (IOL = 50 µA) *Output voltage levels measured with 5 pF load on each output. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Test AD9235BRU-20 AD9235BRU-40 AD9235BRU/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulsewidth High 1 Full V 15.0 8.8 6.2 ns CLK Pulsewidth Low 1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETERS Output Delay 2 (t PD) Full V 3.5 3.5 3.5 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty Jitter (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time 3 Full V 3.0 3.0 3.0 ms OUT-OF-RANGE RECOVERY TIME Full V 1 1 2 Cycles NOTES 1For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. 2Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Specifications subject to change without notice. Figure 1. Timing Diagram tA 2.0ns MIN tPD = 6.0ns MAX N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N ANALOG INPUT CLK DATA OUT N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 |
同様の部品番号 - AD9235BRU-20 |
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同様の説明 - AD9235BRU-20 |
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