STK5DFU350D-E

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11

APPLICATIONS INFORMATION

Input / Output Timing Chart

Figure 14. Input/Output Timing Chart

Notes

1. This section of the timing diagram shows the effect of cross-conduction prevention.

2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low,

switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.

3. This section shows that when the bootstrap voltage VBS drops, the corresponding high side output (U or V or W) is switched off.

When VBS rises sufficiently, normal operation will resume.

4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes

later after the over-current condition is removed.

Input / Output Logic Table

INPUT

OUTPUT

HIN

LIN

Itrip

Enable

High side

IGBT

Low side

IGBT

U,V,W

FAULT

H

L

L

H

ON (Note 5)

OFF

VP

OFF

L

H

L

H

OFF

ON

NU,NV,NW

OFF

L

L

L

H

OFF

OFF

High Impedance

OFF

H

H

L

H

OFF

OFF

High Impedance

OFF

X

X

H

H

OFF

OFF

High Impedance

ON

X

X

X

L

OFF

OFF

High Impedance

OFF