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LM1238 データシート(PDF) 7 Page - National Semiconductor (TI) |
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LM1238 データシート(HTML) 7 Page - National Semiconductor (TI) |
7 / 24 page Typical Performance Characteristics V CC = 5V, TA = 25˚C unless otherwise specified (Continued) Figure 2 and Figure 3 show the case where the Horizontal and Vertical inputs are logic levels. Figure 2 shows the smaller pin 24 voltage superimposed on the horizontal blanking pulse input to the neck board with R H = 4.7K and C 17 = 0.1µF. Note where the voltage at pin 24 is clamped to about 1 volt when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage superimposed on the vertical blank- ing input to the neck board with C 4 jumpered and RV = 4.7K. Figure 4 and Figure 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24 voltage which is derived from a horizontal flyback pulse of 35 volts peak to peak with R H = 8.2K and C17 jumpered. Figure 5 shows the pin 1 voltage which is derived from a vertical flyback pulse of 55 volts peak to peak with C 4 = 1500pF and R V = 120K. Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R 31 = 1K and should be chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9. CATHODE RESPONSE Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is 1.5 nanoseconds. The resulting leading edge has a 10.1 nanosecond risetime and a 8% overshoot, while the trailing edge has a 8.3 nanosecond risetime and a 2% overshoot with an LM2469 driver. ABL GAIN REDUCTION The ABL function reduces the contrast level of the LM1238 as the voltage on pin 22 is lowered from V CC to around 2 volts. Figure 8 shows the amount of gain reduction as the voltage is lowered from V CC (5.0V) to 2V. The gain reduction is small until V 22 reaches the knee anound 3.7V, where the slope increases. Many system designs will require about 3 to 5 dB of gain reduction in full beam limiting. Additional attenu- ation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications. OSD PHASE LOCKED LOOP Table 2 shows the recommended horizontal scan rate ranges (in kHz) for each combination of PLL register setting, 0x081E [1:0], and the pixels per line register setting, 0x0802 [7:6]. While the OSD PLL may lock for other combinations, the performance of the loop will be improved if these recom- mendations are followed. NR means the combination of PLL and PPL is not recommended for any scan rate. TABLE 2. OSD Register Recommendations Pixels per Line PLL Range 130 176 240 352 1 30-45 30-41 30-40 30-41 2 45-89 41-82 40-79 41-82 3 89-100 82-100 79-100 82-100 20038759 FIGURE 7. Red Cathode Response 20038760 FIGURE 8. ABL Gain Reduction Curve www.national.com 7 |
同様の部品番号 - LM1238 |
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同様の説明 - LM1238 |
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