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LM12458CIV データシート(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM12458CIV
部品情報  12-Bit Sign Data Acquisition System with Self-Calibration
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM12458CIV データシート(HTML) 9 Page - National Semiconductor (TI)

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Digital Timing Characteristics (Notes 6, 7, 8, 19) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A+ = VD+ = 5V, tr = tf = 3 ns, and CL =
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for T
A = TJ = TMIN to TMAX; all
other limits T
A = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Unit
(See
Figures 8, 9, 10)
(Note 10)
(Note 11)
(Limit)
17
RD High to TRI-STATE
R
L = 1kΩ
30
10
ns (min)
110
ns (max)
18
RD Low to Data Valid (Access Time)
30
10
ns (min)
80
ns (max)
20
Address Valid or CS Low to RD Low
20
ns (min)
21
Address Valid or CS Low to WR Low
20
ns (min)
19
Address Invalid
10
ns (min)
from RD or WR High
22
INT High from RD Low
30
10
ns (min)
60
ns (max)
23
DMARQ Low from RD Low
30
10
ns (min)
60
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > (VA+orVD+)), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply volt-
ages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction
to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax −TA)/θJA or the num-
ber given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150˚C, and the typical thermal resistance (θJA) of the LM12454 and
LM12(H)458 in the V package, when board mounted, is 47˚C/W, in the W package, when board mounted, is 50˚C/W (
θJC = 5.8˚C/W), and in the EL package, when
board mounted, is 70˚C/W (
θJC = 3.5˚C/W).
Note 5: Human body model, 100 pF discharged through a 1.5 k
Ω resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an
example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.6 VDC to ensure accurate conversions.
Note 7: VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+ pin to assure conversion/
comparison accuracy.
Note 8: Accuracy is guaranteed when operating at fCLK = 5 MHz for the LM12454/8 and fCLK = 8 MHz for the LM12H458.
Note 9: With the test condition for VREF (VREF+ −VREF−) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.
Note 10: Typicals are at TA = 25˚C and represent most likely parametric norm.
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See
Figure 6 Figure 7).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see
Figure 8).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting out-
put value when the inputs are driven with a 2.5V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with VA+ and VD+ at the specified extremes.
Note 16: VREFCM (Reference Voltage Common Mode Range) is defined as (VREF+ +VREF−)/2.
DS011264-3
www.national.com
9


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