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LM12458CIVF データシート(PDF) 10 Page - National Semiconductor (TI) |
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LM12458CIVF データシート(HTML) 10 Page - National Semiconductor (TI) |
10 / 43 page Digital Timing Characteristics (Notes 6, 7, 8, 19) (Continued) Note 17: The LM12(H)454/8’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a repeatability uncertainty of ±0.10 LSB. Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44 clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per con- version. The Throughput Rate is fCLK (MHz)/N, where N is the number of clock cycles/conversion. Note 19: A military RETS specification is available upon request. Electrical Characteristics DS011264-22 VREF = VREF+ −VREF− VIN = VIN+ −VIN− GND ≤ VIN+ ≤VA+ GND ≤ VIN− ≤VA+ FIGURE 1. The General Case of Output Digital Code vs the Operating Input Voltage Range www.national.com 10 |
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同様の説明 - LM12458CIVF |
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