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LM1290 データシート(PDF) 5 Page - National Semiconductor (TI) |
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LM1290 データシート(HTML) 5 Page - National Semiconductor (TI) |
5 / 9 page Pin Descriptions See Figure 4 through Figure 10 for input and output sche- matics. Pin 1 — f MIN: A resistor from this pin to ground sets the free run frequency of the LM1290. The free run frequency should be set typically as: f MIN = 0.85(fMINLOCK)−2kHz where f MINLOCK is the minimum lock frequency required for the application. The resistance required to set this frequency is approximately: For example, to find R MIN for VGA which has fMINLOCK = 31.469 kHz, f MIN = 0.85(31.469 kHz)−2kHz = 24749 Rounding to the closest standard 1% resistor gives R MIN = 21.5 k Ω. Pin 2 — H/HV POLARITY: A 0.1 µF capacitor is connected from this pin to ground for detecting the polarity of H/HV sync at pin 3. A low logic level at pin 2 indicates active-high H/HV sync to pin 3, a high level indicates active-low. See Figure 4 for the output schematic. Pin 3 — H/HV SYNC: This input pin accepts DC-coupled H or composite sync of either polarity. For best noise immunity, a resistor of 2 k Ω or less should be connected from this pin to pin 8 (GND) via a short path. See Figure 5 for the input schematic. Pin 4 — DUTY CYCLE: A DC voltage applied to this pin sets the duty cycle of the H DRIVE output (pin 7), with a range of approximately 30% to 70%. 2V sets the duty cycle to ap- proximately 50%. See Figure 6 for the input schematic. Pin 5 — X-RAY: This pin is for monitoring CRT anode volt- age. If the input voltage exceeds an internal threshold, H DRIVE output (pin 7) is latched high. V CC has to be reduced to below approximately 2V to clear the latched condition, i.e., power must be turned off. See Figure 7 for the input sche- matic. Pin 6 — FLYBACK: Input pin for phase detector 2. For best operation, the flyback peak should be at least 5V but not greater than V CC. Any pulse width greater than 1.5 µs is ac- ceptable. See Figure 8 for the input schematic. Pin 7 — H DRIVE: This is an open-collector output which provides the drive pulse for the high power deflection circuit. The pulse duty cycle is controlled by pin 4. Polarity conven- tion: Horizontal deflection output transistor is on when H DRIVE OUT is low. See Figure 9 for the output schematic. Pin 8 — GND: System ground. For best jitter performance, all bypass capacitors should be connected to this pin via short paths. Pin 9 — PD2 FILTER: The low-pass filter cap of between 0.01 µF to 1 µF for the output of phase detector 2 is con- nected from this pin to pin 8 (GND) via a short path. A smaller value increases the response. Pin 10 — PHASE: A DC control voltage applied to this pin sets the phase of the flyback pulse with respect to the center of H sync. See Figure 10 for the input schematic. Pin 11 — FVC FILTER: A 1 µF capacitor is connected from this pin to pin 8 (GND) via a short path. Pin 12 — PD1 OUT/VCO IN: Phase detector 1 has a gated charge pump output which requires an external low-pass fil- ter. For best jitter performance, the filter should be grounded to pin 8 (GND) via a short path. If a voltage source is applied to this pin, the phase detector is disabled and the VCO can be controlled directly. Pin 13 — V REF: This is the decoupling pin for the internal 8.2V reference. It should be decoupled to pin 8 (GND) via a short path with a cap of at least 470 µF. Do not load this pin. Pin 14 — V CC: 12V nominal power supply pin. This pin should be decoupled to pin 8 (GND) via a short path with a cap of at least 47 µF. Input/Output Schematics DS012917-4 FIGURE 4. DS012917-5 FIGURE 5. www.national.com 5 |
同様の部品番号 - LM1290 |
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同様の説明 - LM1290 |
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