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LM1291N データシート(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM1291N
部品情報  Video PLL System for Continuous-Sync Monitors
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM1291N データシート(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics See Test Circuit(Figure 2) TA e 25 C VCC e 12V (Continued)
Parameter
Conditions
Typical
Limit
Units
(Note 6)
(Note 7)
H Drive duty cycle control
DC input 0V – 4V 30% – 70%
01
TH V
gain
allowed
H Drive Phase control gain
(Note 9)
47
V
PD1 Phase detector leakage current
1
m
A (max)
a
VCO input bias current (Pin 28)
H Drive low level output voltage
IOL e 100 mA
08
V (max)
(Pin 20)
H Drive EN low level input voltage
H Drive output active
08
V (max)
(Pin 15)
H Drive EN high level input voltage
H Drive output open (unlatched)
20
V (min)
(Pin 15)
X-ray Shutdown threshold voltage
Above threshold
172
165
V (min)
(Pin 16)
H Drive Output Open (Latched)
18
V(max)
HHV Sync out
HHV in vs Comp Video in
32
ns
propagation delay change
Clamp Pulse width
(back porch) RSET e 15k VSET e 0V
04
m
s
(back porch) RSET e 15k VSET e 15V
14
m
s
(sync tip) RSET e 15k VSET e 4V
06
m
s
Clamp Pulse Delay
(back porch) Trailing edge HHV Sync In
01
m
s
to leading edge clamp pulse
(sync tip) Leading edge HHV Sync In
0025 TH
s
to leading edge clamp pulse
Internal Ref voltage at pin 6
No load
82
V
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2
Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications
and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics
may degrade when the device is not operated under the listed test conditions
Note 3
All voltages are measured with respect to GND unless otherwise specified
Note 4
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax iJA and the ambient temperature TA The maximum
allowable power dissipation at any elevated temperature is PD e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For
this device TJmax e 150 C The typical thermal resistance (iJA) of these parts when board mounted follow LM1291N 50 CW
Note 5
Human Body model 100 pF capacitor discharged through a 15 kX resistor
Note 6
Typicals are at TA e TJ e 25 C and represent most likely parametric norm
Note 7
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 8
Measured with HP 53310A Modulation Domain Analyzer 50 ms sample window
Note 9
Phase limits b015 k w k
035btDFB
TH
J expressed as a fraction of the horizontal period TH where tDFB is the horizontal output transistor turn-off
delay from the rising edge of H Drive to the FBP peak A positive phase value represents a phase lead of the FBP peak with reference to the leading edge of H
sync
3


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