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LM1292 データシート(PDF) 6 Page - National Semiconductor (TI) |
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LM1292 データシート(HTML) 6 Page - National Semiconductor (TI) |
6 / 10 page Pin Descriptions (Continued) resistor of 2 k Ω or less should be connected from the input side of the coupling cap to pin 21 (GND) via a short path. See Figure 8 for the input schematic. Pin 13 — H DR DUTY CNTL: A DC voltage applied to this pin sets the duty cycle of the horizontal drive output (pin 19), with a range of approximately 30%–70%. 2V sets the duty cycle to 50%. See Figure 9 for the input schematic. Pin 14 — H DRIVE EN : A low logic level input enables H DRIVE OUT (pin 19). See Figure 10 for the input schematic. Pin 15 — X-RAY SHUTDOWN: This pin is for monitoring CRT anode voltage. If the input voltage exceeds an internal threshold, H DRIVE OUT (pin 19) is latched high and VIDEO MUTE (pin 4) is latched low. V CC has to be reduced to below approximately 2V to clear the latched condition, i.e., power must be turned off. See Figure 11 for the input schematic. Pin 16 — V SYNC OUT: The sync processor outputs active-low V sync derived from the active sync input (pin 8, pin 9 or pin 12). Pin 16 stays low in the absence of sync in- put. See Figure 4 for the output schematic. Pin 17 — V CAP: A capacitor is connected from this pin to ground for detecting the polarity and existence of V sync at pin 8. Pin 18 — FLYBACK IN: Input pin for phase detector 2. For best operation, the flyback peak should be at least 5V but not greater than V CC. Any pulse width greater than 1.5 µs is ac- ceptable. See Figure 12 for the input schematic. Pin 19 — H DRIVE OUT: This is an open-collector output which provides the drive pulse for the high power deflection circuit. The pulse duty cycle is controlled by pin 13. Polarity convention: Horizontal deflection output transistor is on when H DRIVE OUT is low. See Figure 5 for the output sche- matic. Pin 20 — H DRIVE GND: Ground return for H DRIVE OUT. For best jitter performance, this pin should be kept separate from the system ground (pin 21); the respective ground traces should meet at a single point, located as close as pos- sible to the power supply output. Pin 21 — GND: System ground. For best jitter performance, all bypass capacitors should be connected to this pin via short paths. Pin 22 — V REF CAP: This is the decoupling pin for the inter- nal 8.2V reference. It should be decoupled to pin 26 (RE- TURN) via a short path with a cap of at least 470 µF. Pin 23 — PHASE DET 2 CAP: The low-pass filter cap for the output of phase detector 2 is connected from this pin to pin 26 (RETURN) via a short path. Pin 24 — H DRIVE PHASE: A DC control voltage applied to this pin sets the phase of the flyback pulse with respect to the leading edge of H sync. See Figure 13 for the input sche- matic. Pin 25 — FVC CAP 1: Primary FVC filter pin. C FVC1 is either connected from this pin to pin 21 (GND) or pin 26 (RETURN) via a short path. The voltage at this pin is buffered to pin 27 (FVC OUT). Pin 26 — RETURN: Ground return for the decoupling ca- pacitor at pin 22 (V REF CAP), the filter capacitor at pin 23 (PHASE DET 2 CAP) as well as the loop filter at pin 28 (PD1 OUT/VCO IN). This pin must be isolated from GND and H DRIVE GND. Pin 27 — FVC OUT: Buffered output of the Frequency-to-Voltage Converter, which sets the VCO center frequency through an external resistor to pin 28. Care should be taken when further loading this pin, since during the ver- tical interval it presents a high output impedance. Excessive loading can cause top-of-screen phase recovery problems. See Figure 14 for the output schematic. Pin 28 — PD1 OUT/VCO IN: Phase detector 1 has a gated charge pump output which requires an external low-pass fil- ter. For best jitter performance, the filter should be grounded to pin 26 (RETURN) via a short path. If a voltage source is applied to this pin, the phase detector is disabled and the VCO can be controlled directly. Application Hints 1. PHASE CONTROL FOR GEOMETRY CORRECTION Pin 24 (H DRIVE PHASE) is designed to control static phase (picture horizontal position), while pin 23 (PHASE DET 2 CAP) controls dynamic phase for geometry correction. With the use of both pins 23 and 24, complete control of static and dynamic phase can be achieved. To accomplish this, the low-pass filter cap at pin 23 is not connected to pin 26 (RE- TURN), but is connected instead to a modulating AC voltage source. The cap then functions both as a low-pass filter (for phase detector 2) and as an input coupling cap (for the AC source). 2. PROGRAMMABLE FREQUENCY RAMPING H frequency transitions from high to low present a special problem for deflection output stages without current limiting. If, during such a transition, the output transistor on-time in- creases excessively before the B+ voltage has decreased to its final level, then the deflection inductor current ramps too high and the induced flyback pulse can exceed the break- down voltage, BV CEX, of the output transistor. To prevent this, the rate of change of the VCO frequency must be lim- ited. Consider a scanning mode transition at t = 0 from f 1 to f2. The VCO frequency as a function of time, f VCO(t), is de- scribed by the equation, f VCO (t) ≈ f1 +(f2 −f1) (1 − exp(−t/τ)), where τ = 40x103 xC FVC1. The above equation can be used to predict VCO behavior during frequency transitions, but in practice the value of C FVC1 is most easily determined empirically. In general, large values minimize the chance of exceeding BV CEX, but generate long PLL capture times. 3. VIDEO MUTE Numerous designs require video blanking during scanning mode transitions. The LM1292 provides an active-low pulse at pin 4 when triggered by a step change of H sync fre- quency from f 1 to f2. The pulse width is controlled by the time constants set up through capacitors C FVC2 and CFVC1,at pins 1 and 25 respectively. For C FVC2 ≥ 3xCFVC1, the pulse width is approximately: Many sync sources fail to exhibit a clean step change of H sync frequency during scanning mode transitions. For this reason, in most applications a pulse smoothing circuit is needed at pin 4. Typically a 2.2 µF cap to ground is used in conjunction with a 100 k Ω pull-up resistor. See Figure 15. The resulting pulse has a slow rise time at the trailing edge, which extends the effective mute duration slightly. www.national.com 6 |
同様の部品番号 - LM1292 |
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同様の説明 - LM1292 |
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