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LM1292N データシート(PDF) 5 Page - National Semiconductor (TI) |
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LM1292N データシート(HTML) 5 Page - National Semiconductor (TI) |
5 / 10 page Block Diagram Pin Descriptions See Figure 4 through Figure 14 for input and output sche- matics. Pin 1 — FVC CAP 2: Secondary FVC filter pin. C FVC2 is con- nected from this pin to ground. The width of the VIDEO MUTE (pin 4) pulse is controlled by the time constant differ- ence between the filters at pins 1 and 25. Pin 2–CLAMP CNTL: This low-impedance current-mode in- put pin is internally biased to 2V. The direction of current sets the pulse position (back porch or sync-tip), while the current magnitude sets the pulse width. In a typical application, a control voltage of 0V–4V is applied to this pin through a 15 k Ω resistor. A voltage below 2V positions the pulse on the back porch of the horizontal sync pulse and decreasing volt- age narrows the pulse. A voltage above 2V sets the pulse on the H sync-tip (slightly delayed from the leading edge) and increasing voltage narrows the pulse. At the boundary of the switchover between the two modes, there is a narrow region of uncertainty resulting in oscillation, which should be no problem in most applications. When there is no H sync in sync-tip mode, the clamp pulse is generated by the VCO at the frequency preset by pin 6 (f MIN). This feature is intended for use in On Screen Display systems. Pin 3 — CLAMP PULSE: Active-low clamp pulse output. See Figure 4 for the output schematic. Pin 4 — VIDEO MUTE: This NPN open-collector output pro- duces an active-low pulse when triggered by a step change of H sync frequency. See Figure 5 for the output schematic. Pin 5 — f MAX: A resistor from this pin to ground sets the up- per frequency limit of the VCO. f MAX is approximately: Pin 6 — f MIN: A resistor from this pin to ground sets the lower frequency limit of the VCO. f MIN is approximately: Pin 7 — V CC: 12V nominal power supply pin. This pin should be decoupled to pin 21 (GND) via a short path with a cap of at least 47 µF. Pin 8 — V SYNC IN: This pin accepts AC-coupled V sync of either polarity. The pin is internally biased at 5.2V; its input resistance is approximately 50 k Ω. For best noise immunity, a resistor of 2 k Ω or less should be connected from the input side of the coupling cap to pin 21 (GND) via a short path. See Figure 6 for the input schematic. Pin 9 — COMP VIDEO IN: The composite video sync strip- per is active only when no signal is present at pin 12 (H/HV IN). The signal to pin 9 must have negative-going sync tips which are at least 0.14V below black level. For best noise im- munity, a resistor of 2 k Ω or less should be connected from the input side of the coupling cap to pin 21 (GND) via a short path. See Figure 7 for the input schematic. Pin 10 — H/HV SYNC OUT: The sync processor outputs active-low H/HV sync derived from the active sync input (pin 9 or pin 12). Pin 10 stays low in the absence of sync input. See Figure 4 for the output schematic. Pin 11 — H/HV CAP: A capacitor is connected from this pin to ground for detecting the polarity and existence of H/HV sync at pin 12. Pin 12 — H/HV SYNC IN: This pin accepts AC-coupled H or composite sync of either polarity. For best noise immunity, a DS012844-3 FIGURE 3. www.national.com 5 |
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同様の説明 - LM1292N |
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