LMV821, LMV824

www.onsemi.com

2

MARKING DIAGRAMS

AAEM

G

G

AAE

= Specific Device Code

M

= Date Code

G

= Pb−Free Package

PIN CONNECTIONS

(Top View)

SC70−5

+IN

−IN

OUTPUT

−

+

2

1

3

5

4

LMV

824

ALYW

G

G

1

14

LMV824 = Specific Device Code

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

LMV824G

AWLYWW

1

14

LMV824 = Specific Device Code

A

= Assembly Location

WL

= Wafer Lot

Y

= Year

WW

= Work Week

G

= Pb−Free Package

1

2

3

4

5

6

7

14

13

12

11

10

9

8

−+

A

+−

D

B

C

OUT A

IN A−

IN A+

V+

IN B+

IN B−

OUT B

OUT D

IN D−

IN D+

V−

IN C+

IN C−

OUT C

SOIC−14

1

2

3

4

5

6

7

14

13

12

11

10

9

8

−+

A

+−

D

B

C

OUT A

IN A−

IN A+

V+

IN B+

IN B−

OUT B

OUT D

IN D−

IN D+

V−

IN C+

IN C−

OUT C

(Top View)

(Top View)

SC−70

SOIC−14

TSSOP−14

(Note: Microdot may be in either location)

(Note: Microdot may be in either location)

TSSOP−14

ORDERING INFORMATION

Order Number

Number of

Channels

Specific Device Marking

Package Type

LMV821SQ3T2G

Single

AAE

SC−70

(Pb−Free)

3000 / Tape & Reel

LMV824DR2G

Quad

LMV824

SOIC−14

(Pb−Free)

2500 / Tape & Reel

LMV824DTBR2G

Quad

LMV

824

TSSOP−14

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.