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MC100E016FNR2G データシート(PDF) 2 Page - ON Semiconductor |
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MC100E016FNR2G データシート(HTML) 2 Page - ON Semiconductor |
2 / 11 page MC10E016, MC100E016 www.onsemi.com 2 1 MR CLK TCLD VEE NC P0 P1 26 27 28 2 3 4 25 24 23 22 21 20 1 918 17 16 15 14 13 12 11 56 7 8 9 10 PE CE P7 P6 P5 VCCO TC Q7 Q6 VCC Q5 Q4 Q3 P2 P3 P4 VCCO Q0 Q1 Q2 VCCO Figure 1. 28-Lead Pinout Assignment (Top View) All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Table 1. PIN DESCRIPTION PIN FUNCTION P0 − P7 Q0 − Q7 CE PE MR CLK TC TCLD NC VCC, VCCO VEE ECL Parallel Data (Preset) Inputs ECL Data Outputs ECL Count Enable Control Input ECL Parallel Load Enable Control Input ECL Master Reset ECL Clock ECL Terminal Count Output ECL TC−Load Control Input No Connect Positive Supply Negative Supply Figure 2. 8-Bit Binary Counter Logic Counter Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. P1 SLAVE MASTER 5 TC Q1 Q0 P7 Q6 Q5 Q4 Q3 Q2 Q1 CE Q0 BIT 1 CE Q0 Q0M Q0M BIT 0 PE TCLD CE PO MR CLK BIT 7 BITS 2-6 Q7 Table 2. FUNCTION TABLE FUNCTION CE PE TCLD MR CLK Load Parallel (Pn to Qn) X L X L Z Continuous Count L H L L Z Count; Load Parallel on TC = LOW L H H L Z Hold H H X L Z Masters Respond, Slaves Hold X X X L ZZ Reset (Qn : = LOW, TC : = HIGH) X X X H X Z = clock pulse (low to high); ZZ = clock pulse (high to low) |
同様の部品番号 - MC100E016FNR2G |
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