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MC10EP33 データシート(PDF) 2 Page - ON Semiconductor

部品番号 MC10EP33
部品情報  Divider
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MC10EP33, MC100EP33
www.onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
CLK
Q
CLK
VBB
RESET
R
B4
Table 1. PIN DESCRIPTION
PIN
CLK*, CLK*
Reset*
ECL Asynchronous Reset
FUNCTION
ECL Clock Inputs
Table 2. TRUTH TABLE
CLK
X
Z
CLK
X
Z
RESET
Z
L
Q
L
F
Q
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
EP
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnected,
floating open.
Figure 2. Timing Diagram
CLK
RESET
Q
tRR
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
NA
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb-Free Pkg
SOIC−8 NB
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
Transistor Count
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.


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