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LM1893 データシート(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM1893
部品情報  LM1893/LM2893 Carrier-Current Transceiver
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM1893 データシート(HTML) 3 Page - National Semiconductor (TI)

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Receiver Electrical Characteristics (Note 3) The test conditions are Vae18 V FOe125 kHz g22%
deviation FSK FDATAe24 kHz VINe100 mVpp in the receive mode unless otherwise noted
Test
Design
Limit
Parameter
Conditions
Typical
Limit
Limit
Units
(Note 4)
(Note 5)
25
Supply voltage V
a
range
Functional receiver (Note 7)
12
13
135
V min
37
30
28
V max
26
Supply current IQT
IQT is pin 15 (V
a ) plus pin 10
11
5
mA min
(Carrier IO) current 24 kX Pin 13 to GND
14
mA max
27
Carrier IO input resistance R10
Pin 10
195
14
kX min
30
kX max
28
Max data rate FMD
Functional receiver (Note 7) CF e 100 pF
10
48
24
kBaud
RF e 0X no tank
24 kHze48 kBaud
29
PLL capture range FC
CFe100 pF RFe0 X
g
40
g
15
g
10
% min
30
PLL lock range FL
CFe100 pF RFe0 X
g
45
g
15
% min
31
Receiver input sensitivity SIN
For a functional receiver (Note 8)
Referred to chip side (pin 10)
18
10
12
mVRMS
of the line-coupling XFMR FOe50 kHz
20
mVRMS
FOe300 kHz
14
mVRMS
Referred to line side of XFMR
026
mVRMS
(assuming a 7071 XFMR) FOe50 kHz
029
mVRMS
FOe300 kHz
020
mVRMS
32
Tolerable input dc voltage offset
Pin 10 lower than pin 15 by VINDC
2
01
V max
range VINDC
33
Data Out breakdown voltage
Pin 12 leakage Is20 mA
70
55
V min
34
Data Out low output VOL
Pin 12 sat voltage at IOLe2 mA
015
04
V max
35
Impulse noise filter current II
Pin 13 charge and discharge current
g
55
g
45
m
A min
g
85
m
A max
36
Offset hold cap bias voltage VCM
Pin 6
20
13
V min
35
V max
37
Offset hold capacitor max drive
Pin 6 V(pin 3)bV(pin 4)e g250 mV
g
55
g
25
m
A min
current IMCM
g
80
m
A max
38
Offset hold bias current IOHB
Pin 6 TX mode Bias pin 6 as it self-
b
05
b
20
b
40
nA min
biased during test 31
40
nA max
39
Phase comparator current IPC
Bias pins 3 and 4 at 85 V
100
50
m
A min
IPCeI(pin 3) a I(pin 4) TX mode
200
m
A max
40
Phase detector output resistance
Pins 3 and 4
10
6
kX min
RPD
RPDe(V 100mAbV 50mA)(50mA)
18
kX max
41
Phase detector demodulated output
Pin 3 to 4 measured after filtering
100
60
mVpp min
voltage VPD
out the 2FO component
180
mVpp max
42
Fast offset cancel voltage ‘‘window’’
VPIN3bVPIN4 e gVWINDOW a DC offset
095
070
VV min
-to-VPD ratio VW VPD
Drive for g1 mA pin 6 current
120
VV max
43
Power supply rejection PSRR
CL e 01 mF PSRR e CMRR 120 Hz
80
dB min
Note 1
More accurately the maximum voltage allowed on pin 10 is VOC and VOC ranges from 41 to 50V Also transients may reach above 60V see the transient
peak voltage characteristic curve
Note 2
The maximum power dissipation rating should be derated for device operation above 25 C to insure that the junction temperature remains below the
maximum rating Use a iJA of 75 CW for the N package using a socket in still air (which is the worst case) Consult the Application Information section for more
detail
Note 3
The boldface values apply over the full junction temperature range for the specified supply voltage range All other numbers apply at TAeTJe25 C Pin
numbers refer to LM1893 LM2893 tested by shorting Carrier In to Carrier Out and testing it as an LM1893
Note 4
Guaranteed and 100% production tested
Note 5
Guaranteed (but not 100% production tested) over the temperature and supply voltage ranges These limits are not used to calculate outgoing quality
levels
Note 6
Total harmonic distortion is measured using THDe IRMS (all components at or above 2FO)
IRMS (fundamental)
Note 7
Receiver function is defined as the error-free passage of 1 cycle of 50% duty-cycle 24 kHz square-wave data (2 sequential 208 mS bits) with the first bit
being a ‘‘1’’ All of the data transitions (edges) must fall within g10% (g208 ms) of their noise-free positions RX time delay is minimized by using no impulse noise
filter cap CI for this test
Note 8
During the sensitivity check note 7 requirements are followed with these exceptions (1) data rate FDATAe12 kHz (2) all of the data transitions must fall
within g20% (g416 ms) of their noise-free positions and (3) a time-domain filter capacitor (CI) is used The time delay of CI is
bit or 208 ms (CI is
approximately 6200 pF)
Note 9
For TTL compatibility use a pull-up resistor to increase min VOH to above 28 V
3


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