4 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
External Memory Interface
The Ultimate 3000 Radio Processor is a true single chip device and does not require additional memory for standard
below HCI protocol functions. An external memory interface is available for adding optional memory. If external Flash
memory will be used, the read access time of the device must be 100 ns or less.
The external memory interface permits connection to Flash and SRAM devices. The interface has an 18-bit address bus
and a 16-bit data bus for a total addressable memory of 512 KB. In certain embedded applications, both SRAM and
Flash can be installed by using the high order address bit as an alternate chip select.
External EEPROM Controller and Interface
This interface is intended for use with ROM-based solutions. The EEPROM is not required for configurations with exter-
nal flash. The EEPROM is the non-volatile memory (NVM) in the system and contains the system configuration parame-
ters such as the Bluetooth device address, the CODEC type, as well as other parameters. These default parameters are
set at the factory, and some parameters will change depending on the system configuration. Optionally, the non-volatile
memory parameters can be downloaded from the host processor at boot up eliminating the need for EEPROM. Please
consult the application support team for details. The EEPROMs should have a serial I2C interface with a minimum size of
2 Kbits and 16-byte page write buffer capabilities.
Power Management
The HOST_WAKEUP and EXT_WAKE signals are used for power management. HOST_WAKEUP is an output signal
used to wake up the host. EXT_WAKE is an input signal used by the host to wake up the SiW3000 Radio Processor from
sleep mode. For more information on the usage of HOST_WAKE and EXT_WAKE, please refer to RFMD application
note 62 0031.
PIO#
Shared I/O
Sampled at Reset
PIO#
Shared I/O
Sampled at Reset
0
None
Yes
15
PCM_OUT
No
1
None
Yes
16
PCM_IN
No
2
None
Yes
17
PCM_CLK
No
3
D[8]
No
18
PCM_SYNC
No
4
D[4]
No
19
EXT_WAKE
No
5
D[5]
No
20
HOST_WAKEUP
No
6
D[6]
No
21
UART_RXD
No
7
D[7]
No
22
UART_TXD
No
8
PWR_REG_EN
No
23
UART_CTS
No
9
D[15]
No
24
UART_RTS
No
10
WE_N
No
25
A[18]
No
11
A[16]
No
26
TX_RX_SWITCH
No
12
A[17]
No
27
D[9]
No
13
A[11]
No
28
D[10]
No
14
USB_DPLS_PULLUP
No
Signal
Description
Address A[1] - A[18]
18-bit address bus
Data D[0] - D[15]
16-bit data bus
FCS_N
Chip select
OE_N
Output enable
WE_N
Write enable
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
