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NBSG86A データシート(PDF) 10 Page - ON Semiconductor

部品番号 NBSG86A
部品情報  2.5V/3.3V SiGe Differential Smart Gate with Output Level Select
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NBSG86A データシート(HTML) 10 Page - ON Semiconductor

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Table 13. AC CHARACTERISTICS
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
−40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Input Clock Frequency
(See Figure 7) (Note 26)
7
8
7
8
7
8
GHz
VOUTPP
Output Voltage Amplitude
fin v 7 GHz
(OLS = VCC)fin = 8 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
mV
tPLH,
tPHL
Propagation Delay to Output Differential
(Figure 16)
D/SEL
→ Q
110
160
210
115
165
215
120
170
220
ps
tSKEW
Duty Cycle Skew (Note 27)
5
15
5
15
5
15
ps
tSKEW
Channel Skew
Q
→ D/SEL
5
20
5
20
5
20
ps
tS
Set−Up Time (Dx to SEL)
30
30
30
ps
tH
Hold−Up Time (Dx to SEL)
35
35
35
ps
tJITTER
RMS Random Clock Jitter
(See Figure 7) (Note 29)
fin v 7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 30)
fin v 7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% − 80%)
(Q, Q)
tr
@ 1 GHz
tf
30
17
45
35
60
65
30
17
45
35
60
65
30
17
45
35
60
65
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
26. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
27. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. See Figure 16.
28. VINPP (max) cannot exceed VCC − VEE.
29. Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
30. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data rate at 7 Gb/s.


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