CDCLVP111-EP datasheet(7/23 Pages) TI1

部品番号	CDCLVP111-EP

部品情報	Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

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CLKn

Q0

Q1

Q2

Q9

CLKn

Q0

Q1

Q2

Q9

tPLH2

tPLH1

tPLH0

tPLH9

Continuous TJ (°C)

85

95

105

115

125

135

145

150

1

10

100

D001

Electromigration Fail Mode

7

CDCLVP111-SP

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SCAS946 – NOVEMBER 2016

Product Folder Links: CDCLVP111-SP

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(1)

See data sheet for absolute maximum and minimum recommended operating conditions.

(2)

Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect

life).

Figure 1. CDCLVP111-SP Operating Life Derating Chart

A.

Output skew is calculated as the greater of: the difference between the fastest and the slowest tPLHn (n = 0, 1,...9) or

the difference between the fastest and the slowest tPHLn (n = 0, 1,...9).

B.

Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0,

1,...9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9) across

multiple devices.

C.

Typical value measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz.

D.

Input conditions: VCM = 1 V, VID = 0.5 V and FIN = 1 GHz.

Figure 2. Waveform for Calculating Both Output and Part-to-Part Skew

同様の部品番号 - CDCLVP111-EP

メーカー	部品番号	データシート	部品情報
Texas Instruments	CDCLVP111-EP	743Kb / 15P	[Old version datasheet] LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER

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同様の説明 - CDCLVP111-EP

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Texas Instruments	CDCLVP111-EP	743Kb / 15P	[Old version datasheet] LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER
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