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BU2396KN データシート(PDF) 2 Page - Rohm |
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BU2396KN データシート(HTML) 2 Page - Rohm |
2 / 24 page BU2396KN 2/20 TSZ02201-0E3E0J500710-1-2 © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 04.Nov.2015 Rev.001 Block Diagram and Pin Configuration Pin Descriptions Pin No. Pin Name Function 1 AVDD Analog power source 2 AVDD Analog power source 3 AVSS Analog GND 4 XIN Crystal IN 5 XOUT Crystal OUT 6 TEST TEST pin, normally open, equipped with pull-down 7 TGCLK_SEL2 TGCLK frequency selection, equipped with pull-up 8 TGCLK_SEL1 TGCLK frequency selection, equipped with pull-up 9 TGCLK_PD TGCLK Power-Down control, H:enable, L:Power-Down, equipped with pull-down 10 TGCLK_EN TGCLK output control, H: Enable, L: Output fixed to L, equipped with pull-down 11 TGCLK 36M, 30M, 24M output 12 VCLK_EN VCLK output control, H:enable, L: Output fixed to L, equipped with pull-down 13 VSS1 TGCLK,UCLK & Internal digital GND 14 VDD1 TGCLK,UCLK & Internal digital power supply 15 VDD1 TGCLK,UCLK & Internal digital power supply 16 UCLK 12M output 17 VSS2 VCLK GND 18 VDD2 VCLK power source 19 VCLK 27M output 20 VCLK_PD VCLK Power-Down control, H:enable, L:Power-Down, equipped with pull-down (Note) Basically, mount ICs to the printed circuit board for use. If the ICs are not mounted to the printed circuit board, the characteristics of ICs may not be fully demonstrated. Mount 0.1µF as bypass capacitors near IC pins between PIN 1&2 and PIN 3, PIN 13 and PIN 14&15, and PIN 17 and PIN 18 respectively. As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Also, the operating margin should be thoroughly checked. PLL1 PLL2 DATA XTAL OSC XOUT XIN TGCLK_EN TGCLK_SEL2 TGCLK_SEL1 TGCLK_PD VCLK_PD VCLK_EN UCLK TGCLK VCLK 4 5 10 7 8 9 20 12 16 11 19 30.000000MHz 24.000000MHz 36.000000MHz 12.000000MHz 27.000000MHz 1/6 1/8 TOP VIEW |
同様の部品番号 - BU2396KN_15 |
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同様の説明 - BU2396KN_15 |
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