S25FL256S datasheet(95/149 Pages) CYPRESS

部品番号	S25FL256S

部品情報	128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

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95 / 149 page

Document Number: 001-98283 Rev. *J

Page 95 of 149

S25FL128S/S25FL256S

9.4.8

DDR Dual I/O Read (BDh, BEh)

The instruction



BDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or



BDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or



BEh is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out, in a DDR fashion, two bits at a time on each clock edge through IO0

(SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by the rising and falling edge of the SCK signal.

The DDR Dual I/O Read command improves throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar to the Dual I/O

Read command but transfers two address, mode, or data bits on every edge of the clock. In some applications, the reduced

instruction overhead might allow for code execution (XIP) directly from S25FL128S and S25FL256S devices.

The maximum operating clock frequency for DDR Dual I/O Read command is 80 MHz.

For DDR Dual I/O Read commands, there is a latency required after the last address bits are shifted into IO0 and IO1, before data

begins shifting out of IO0 and IO1. There are different ordering part numbers that select the latency code table used for this

command, either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The number of

latency (dummy) clocks is determined by the frequency of SCK (refer to Table 7.12, Latency Codes for DDR High Performance

on page 51

or Table 7.14, Latency Codes for DDR Enhanced High Performance on page 51). The number of dummy cycles is set

by the LC bits in the Configuration Register (CR1).

The HPLC table does not provide cycles for mode bits so each Dual I/O command starts with the 8 bit instruction, followed by

address, followed by a latency period. This latency period allows the device’s internal circuitry enough time to access the initial

address. During these latency cycles, the data value on SI (IO0) and SO (IO1) are “don’t care” and may be high impedance. When

the Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals

must be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.

The EHPLC table does provide cycles for mode bits so a series of Dual I/O DDR commands may eliminate the 8 bit instruction after

the first command sends a complementary mode bit pattern, as shown in Figure 9.47 and Figure 9.49 on page 96. This added

feature removes the need for the eight bit SDR instruction sequence and dramatically reduces initial access times (improves XIP

performance). The Mode bits control the length of the next DDR Dual I/O Read operation through the inclusion or exclusion of the

first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah)

the device transitions to Continuous DDR Dual I/O Read Mode and the next address can be entered (after CS# is raised high and

then asserted low) without requiring the BDh or BEh instruction, as shown in Figure 9.48 on page 96, and thus, eliminating eight

cycles from the command sequence. The following sequences will release the device from Continuous DDR Dual I/O Read mode;

after which, the device can accept standard SPI commands:

1. During the DDR Dual I/O Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised

high and then asserted low the device will be released from DDR Dual I/O Read mode.

2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1) are not set

for a valid instruction sequence, then the device will be released from DDR Dual I/O Read mode.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. The HOLD function is not

valid during Dual I/O DDR commands.

Note that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is a data learning pattern

(DLP) that is used by the host controller to optimize data capture at higher frequencies. The preamble DLP drives the IO bus for the

four clock cycles immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the

memory starts outputting the preamble.

同様の部品番号 - S25FL256S

メーカー	部品番号	データシート	部品情報
SPANSION	S25FL256S	5Mb / 153P	MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
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	S25FL256SAGBFI001	5Mb / 153P	MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL256SAGBFIG11	5Mb / 153P	MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL256SAGBHIG13	5Mb / 153P	MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

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同様の説明 - S25FL256S

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