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CAT24C02VP2E.GT3 データシート(PDF) 4 Page - ON Semiconductor |
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CAT24C02VP2E.GT3 データシート(HTML) 4 Page - ON Semiconductor |
4 / 23 page CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16 www.onsemi.com 4 Table 5. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol Parameter Conditions Max Units CIN (Note 4) SDA Pin Capacitance VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 8 pF Other Pins 6 pF IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA VIN < VIH, VCC = 3.3 V 120 VIN < VIH, VCC = 1.7 V 80 VIN > VIH 2 IA (Note 5) Address Input Current (A0, A1, A2) Product Rev H: CAT24C02 Product Rev K: CAT24C04, CAT24C08, CAT24C16 VIN < VIH, VCC = 5.5 V 50 mA VIN < VIH, VCC = 3.3 V 35 VIN < VIH, VCC = 1.7 V 25 VIN > VIH 2 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. Table 6. A.C. CHARACTERISTICS (Note 6) (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.) Symbol Parameter Standard Fast Units Min Max Min Max FSCL Clock Frequency 100 400 kHz tHD:STA START Condition Hold Time 4 0.6 ms tLOW Low Period of SCL Clock 4.7 1.3 ms tHIGH High Period of SCL Clock 4 0.6 ms tSU:STA START Condition Setup Time 4.7 0.6 ms tHD:DAT Data In Hold Time 0 0 ms tSU:DAT Data In Setup Time 250 100 ns tR SDA and SCL Rise Time 1000 300 ns tF (Note 6) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time 4 0.6 ms tBUF Bus Free Time Between STOP and START 4.7 1.3 ms tAA SCL Low to Data Out Valid 3.5 0.9 ms tDH Data Out Hold Time 100 100 ns Ti (Note 6) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns tSU:WP WP Setup Time 0 0 ms tHD:WP WP Hold Time 2.5 2.5 ms tWR Write Cycle Time 5 5 ms tPU (Notes 7, 8) Power−up to Ready Mode 1 1 ms 6. Test conditions according to “AC Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. |
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