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CS89712 データシート(PDF) 9 Page - Cirrus Logic |
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CS89712 データシート(HTML) 9 Page - Cirrus Logic |
9 / 170 page CS89712 DS502PP2 9 (i.e., the main batteries are low), corresponding to a low level on nPWRFL or BATOK. From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock run- ning, the CS89712 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point. After the first clock is ap- plied, there will be a delay of about eight clock cy- cles before the CPU is enabled. This delay allows the CPU clock to settle. 2.2.1.1 UART in Standby State During the Standby State, the UARTs are disabled and cannot detect any activity (i.e., start bit) on the receiver. If this functionality is required then this can be accomplished in software by the following method: 1) Permanently connect the RX pin to one of the active low external interrupt pins. 2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the UART is enabled. 3) Send a preamble that consists of one start bit, 8 bits of zero, and one stop bit. This will cause the CS89712 to wake and execute the enabled interrupt vector. The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the start of the preamble, the timing of the sample point will be off-center during the pre- amble byte. However, the next byte transmitted will be correctly aligned. Thus, the actual first real byte to be received by the UART will be correct. 2.2.2 Idle State If in the Operating State, the Idle State can be en- tered by writing to a special internal memory loca- tion (HALT) in the CS89712. If an interrupt occurs, the CS89712 will return immediately back to the Operating State and execute the next instruction. The WAKEUP signal can not be used to exit the Idle State. It is only used to exit the Standby State. In the Idle State, the device functions just like it does when in the Operating State. However, the CPU clock is halted while it waits for an event such as a key press to generate an interrupt. The PLL al- ways remains active in the Idle State. 2.2.3 Keyboard Interrupt Wakeup For the case of the keyboard interrupt, the follow- ing options are available and are selectable accord- ing to bits 1 and 3 of the SYSCON2 register (refer to Section 3.5.2 for register details). • If the KBWEN bit (SYSCON2 bit 3) is set low, then a keypress will cause a transition from a power saving state only if the keyboard inter- rupt is non-masked (i.e., the interrupt mask reg- ister 2 (INTMR2 bit 0) is high). • When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the “Keyboard Direct Wakeup’ mode. In this mode, the interrupt request may not get ser- viced. If the interrupt is masked (i.e., the inter- rupt mask register 2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off before it entered the pow- er saving state. If the interrupt is non-masked, then the processor will service the interrupt. • When the KBD6 bit (SYSCON2 bit 1) is low, all 8 Port A inputs are OR’ed together to pro- duce the internal wakeup signal and keyboard interrupt request. This is the default reset state. • When the KBD6 bit (SYSCON2 bit 1) is high, only the lowest 6 bits of Port A are OR’ed to- gether to produce the internal wakeup signal and keyboard interrupt request. The two most significant bits of Port A are available as GPIO when this bit is set high. |
同様の部品番号 - CS89712 |
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同様の説明 - CS89712 |
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