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6V49205B データシート(PDF) 6 Page - Integrated Device Technology

部品番号 6V49205B
部品情報  Freescale System Clock w/Selectable DDR Frequency
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

6V49205B データシート(HTML) 6 Page - Integrated Device Technology

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FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY
6
REVISION R 11/23/16
6V49205B DATASHEET
AC Electrical Characteristics - Low Power HCSL-Compatible PCIe Outputs
Electrical Characteristics - Phase Jitter, PCIe Outputs at 100MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
MHz
2,3
MHz
2,3
ppmSSoff
PCIe 100MHz or 125MHz
ppm
1,2
ppmSSon
PCIe @ -0.5% spread, 100MHz only
ppm
1,2
Rising/Falling Edge Slew Rate
tSLEW
Differential Measurement
2.2
4.1
5.7
V/ns
1,3,6
Slew Rate Variation
tSLVAR
Single-ended Measurement
1
20
%
1,6
Maximum Output Voltage
VHIGH
Includes overshoot
793
1150
mV
6,7
Minimum Output Voltage
VLOW
Includes undershoot
-300
-22
mV
6,7
Differential Voltage Swing
VSWING
Differential Measurement
300
mV
1,6
Crossing Point Voltage
VXABS
Single-ended Measurement
300
419
550
mV
1,4,6
Crossing Point Variation
VXABSVAR
Single-ended Measurement
115
140
mV
1,4,5
Duty Cycle
DCYC
Differential Measurement
45
50.1
55
%
1
PCIe Jitter - Cycle to Cycle
PCIeJC2C
Differential Measurement
36
125
ps
1
PCIe[5:0] Skew
TSKEwPCIe50
Differential Measurement
1172
1500
ps
1,6,8
Spread Spectrum Modulation
Frequency
fSSMOD
Triangular Modulation
30
31.5
33
kHz
Notes for PCIe Clocks:
1 Guaranteed by design and characterization, not 100% tested in production.
2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz
3 Slew rate measured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#.
5 Only applies to the differential rising edge (Clock rising, Clock# falling.)
6 At default SMBus settings.
7 The Freescale P-series CPU's have internal terminations on their SerDes Reference Clock inputs. The resulting amplitude at these inputs will be 1/2 of the
values listed, which are well within the 800mV Freescale specification for these inputs.
8 This value includes an intentional output-to-output skew of approximately 250ps.
Synthesis error
0
+/-100
Clock Frequency
f
Spread off
100.00
125.00
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
INDUSTRY
SPEC LIMIT UNITS NOTES
tjphPCIe1
PCIe Gen 1 phase jitter
35
56
86
ps
1,2,3
tjphPCIe2Lo
PCIe Gen 2 phase jitter
Lo-band content
1.6
2.4
3
ps
(RMS)
1,2,3
tjphPCIe2Hi
PCIe Gen 2 phase jitter
Hi-band content
1.9
2.8
3.1
ps
(RMS)
1,2,3
tjphPCIe3
PCIe Gen 3 phase jitter
0.5
0.83
1
ps
(RMS)
1,2,3
Notes on Phase Jitter:
2 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12
3 Applies to PCIe outputs @ default amplitude and 100MHz with spread off or at -0.5%.
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.
Jitter, Phase


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