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CS8401A-IS データシート(PDF) 7 Page - List of Unclassifed Manufacturers

部品番号 CS8401A-IS
部品情報  Digital Audio Interface Transmitter
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CS8401A-IS データシート(HTML) 7 Page - List of Unclassifed Manufacturers

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GENERAL DESCRIPTION
The CS8401A/2A are monolithic CMOS circuits
that encode and transmit audio and digital data
according to the AES/EBU, IEC 958 (S/PDIF),
and EIAJ CP-340 interface standards. Both chips
accept audio and control data separately; multi-
plex an d b i phase- mark enco de the d ata
internally; and drive it, directly or through a
transformer, to a transmission line. The CS8401A
is fully software programmable through a paral-
lel port and contains buffer memory for control
data, while the CS8402A has dedicated pins for
the most important control bits and a serial input
port for the C, U, and V bits.
Familiarity with the AES/EBU and IEC 958
specifications are assumed throughout this data
sheet. Many terms such as channel status, user
data, auxiliary data, professional mode, etc. are
not defined. The Application Note, Overview of
AES/EBU Digital Audio Interface Data Struc-
tures, provides an overview of the AES/EBU and
IEC 958 specifications and is included for clar-
ity; however, it is not meant to be a complete
reference, and the complete standards should be
obtained from the Audio Engineering Society or
ANSI for the AES/EBU document, and the Inter-
national Electrotechnical Commission for the
IEC document.
Line Drivers
The RS422 line drivers for both the CS8401A
and CS8402A are low skew, low impedance, dif-
ferential outputs capable of driving 110
transmission lines with a 4 volt peak-to-peak sig-
nal when configured as shown in Appendix A.
To prevent possible short circuits, both drivers
are set to ground when no master clock (MCK)
is provided. They can also be disabled by reset-
ting the device (RST = low). Appendix A
contains more information on the line drivers. A
0.1
µF capacitor, with short leads, should be
placed as close as possible to the VD+ and GND
pins.
CS8401A DESCRIPTION
The CS8401A accepts 16- to 24-bit audio samples
through a configurable serial port, and channel status,
user, and auxiliary data through an 8-bit parallel port.
The parallel port allows access to 32 bytes of internal
memory which is used to store control information
and buffer channel status, user, and auxiliary data.
This data is multiplexed with the audio data from the
serial port, the parity bit is generated, and the bit
stream is biphase-mark encoded and driven through
an RS422 line driver. A block diagram of the
CS8401A is shown in Figure 4. In accordance with
the professional definition of channel status, the
CRCC code (C.S. byte 23) can be internally gener-
ated.
Parallel Port
The parallel port accesses one status register, three
control registers, and 28 bytes of dual port buffer
memory. The address bus, and RD/WR line must be
valid when CS goes low. If RD/WR is low, the value
on the data bus will be written into the buffer mem-
ory at the specified address. If RD/WR is high, the
value in the buffer memory, at the specified address,
is placed on the data bus. The detailed timing for
reading and writing the CS8401A can be found in
the Digital Switching Characteristics table. The
memory space is allocated as shown in Figure 5.
There are three defined buffer memory modes select-
able by two bits in control register 2.
Status and Control Registers
Upon power up the CS8401A control registers
contain all zeros. Therefore, the part is initially
in reset and is muted. One’s must be written to
control register 2, bits RST and MUTE, before
the part will transmit data. The remaining regis-
ters are not initialized on power-up and may
contain random data.
The first register, shown in Figure 6, is the status
register in which only three bits are valid. The lower
three bits contain flags indicating the position of the
transmit pointer in the buffer memory. These flags
CS8401A CS8402A
DS60F1
7


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