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MC14024B データシート(PDF) 1 Page - ON Semiconductor |
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MC14024B データシート(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 10 1 Publication Order Number: MC14024B/D MC14024B 7-Stage Ripple Counter The MC14024B is a 7−stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered. Features • Diode Protection on All Inputs • Output Transitions Occur on the Falling Edge of the Clock Pulse • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range • Pin−for−Pin Replacement for CD4024B • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range −0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) −0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com MARKING DIAGRAM SOIC−14 D SUFFIX CASE 751A 1 14 14024BG AWLYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION 11 12 13 14 8 9 10 5 4 3 2 1 7 6 NC Q2 Q1 NC VDD NC Q3 Q6 Q7 RESET CLOCK VSS Q4 Q5 PIN ASSIGNMENT VDD = PIN 14 VSS = PIN 7 NC = NO CONNECTION |
同様の部品番号 - MC14024B_14 |
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同様の説明 - MC14024B_14 |
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