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LM2725M データシート(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM2725M
部品情報  High Speed Synchronous MOSFET Drivers
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM2725M データシート(HTML) 3 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC
7.5V
CBOOT
42V
CBOOT to SW
8V
SW to PGND
36V
Junction Temperature
+150˚C
Power Dissipation
(Note 2)
720mW
Storage Temperature
−65˚ to 150˚C
ESD Susceptibility
Human Body Model (Note 3)
1 kV
Soldering Time, Temperature
10sec., 300˚C
Operating Ratings (Note 1)
VCC
4V to 7V
Junction Temperature Range
0˚ to 125˚C
Electrical Characteristics
LM2725
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T
A
=T
J = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
POWER SUPPLY
I
q_op
Operating Quiescent
Current
PWM_IN = 0V
180
250
µA
I
q_sd
Shutdown Quiescent
Current
EN = 0V, PWM_IN = 0V
0.5
15
µA
TOP DRIVER
Peak Pull-Up Current
Test Circuit 1, V
bias = 5V,
R = 0.1
1.2
A
Pull-Up Rds_on
I
CBOOT =IHG = 0.7A
2.4
Peak Pull-down Current
Test Circuit 2, V
bias = 5V,
R = 0.1
−1.0
A
Pull-down Rds_on
I
SW =IHG = 0.7A
1.4
t
4
Rise Time
Timing Diagram, C
LOAD =
3.3nF
17
ns
t
6
Fall Time
10
ns
t
3
Pull-Up Dead Time
Timing Diagram
23
ns
t
5
Pull-Down Delay
Timing Diagram, from
PWM_IN Falling Edge
21
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, V
bias = 5V,
R = 0.1
1.2
A
Pull-up Rds_on
I
VCC =ILG = 0.7A
2.6
Peak Pull-down Current
Test Circuit 4, V
bias = 5V,
R = 0.1
−2
A
Pull-down Rds_on
I
GND =ILG = 0.7A
0.65
t
8
Rise Time
Timing Diagram, C
LOAD =
3.3nF
18
ns
t
2
Fall Time
6
ns
t
7
Pull-up Dead Time
Timing Diagram
28
ns
t
1
Pull-down Delay
Timing Diagram, from
PWM_IN Rising Edge
15
ns
LOGIC
V
uvlo_up
Power On Threshold
VCC rises from 0V toward
5V
3.0
V
V
uvlo_dn
Under-Voltage-Lock-Out
Threshold
2.5
V
V
uvlo_hys
Under-Voltage-Lock-Out
Hysteresis
0.5
V
www.national.com
3


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