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MC74AC74DG データシート(PDF) 1 Page - ON Semiconductor |
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MC74AC74DG データシート(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 8 1 Publication Order Number: MC74AC74/D MC74AC74, MC74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features • Outputs Source/Sink 24 mA • ′ACT74 Has TTL Compatible Inputs • These are Pb−Free Devices CP1 CD2 CP2 13 14 12 11 10 9 8 2 1 3 4 567 VCC CD1 D1 CP1 SD1 Q1 Q1 CD2 D2 CP2 SD2 Q2 Q2 CD1 SD1 Q1 D1 SD2 Q2 Q2 D2 GND Q1 Figure 1. Pinout: 14−Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN FUNCTION D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION www.onsemi.com MARKING DIAGRAMS xxx = AC or ACT A = Assembly Location WL or L = Wafer Lot Y = Year WW or W = Work Week G or G = Pb−Free Package TSSOP−14 DT SUFFIX CASE 948G xxx 74 ALYW G G 1 14 SOIC−14 D SUFFIX CASE 751A 1 14 1 14 xxx74G AWLYWW 1 14 (Note: Microdot may be in either location) |
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