データシートサーチシステム |
|
TLS805B1SJV データシート(PDF) 5 Page - Infineon Technologies AG |
|
TLS805B1SJV データシート(HTML) 5 Page - Infineon Technologies AG |
5 / 26 page Data Sheet 5 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Pin Configuration 3 Pin Configuration 3.1 Pin Assignment in PG-DSO-8 Package Figure 4 Pin Configuration TLS805B1 in PG-DSO-8 package 3.2 Pin Definitions and Functions in PG-DSO-8 Package Pin Symbol Function 1I Input It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. 2N.C. Not connected 3EN Enable Integrated pull-down resistor. Enable the IC with high level input signal. Disable the IC with low level input signal. 4GND Ground 5N.C. Not connected 6N.C. Not connected 7ADJ Voltage Adjustment Connect an external voltage divider to determine the output voltage. 8Q Output Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in Table 2 “Functional Range” on Page 9. Q ADJ N.C. I N.C. EN GND N.C. 1 3 2 8 7 6 45 |
同様の部品番号 - TLS805B1SJV |
|
同様の説明 - TLS805B1SJV |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |