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DAC38RFxx データシート(PDF) 6 Page - Texas Instruments |
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DAC38RFxx データシート(HTML) 6 Page - Texas Instruments |
6 / 152 page 6 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3 – DECEMBER 2016 www.ti.com Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions - DAC38RF83, DAC38RF93, DAC38RF85 (continued) PIN I/O DESCRIPTION NAME NO. SYNC1- C6 O Synchronization request to transmitter for JESD204B link 1, LVDS negative output. SYSREF+ A3 I LVPECL SYSREF positive input. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization. SYSREF- A4 I LVPECL SYSREF negative input. (See the SYSREF description) TCLK K4 I JTAG test clock. TDI H4 I JTAG test data in. TDO J4 O JTAG test data out. TESTMODE K3 - This pin is used for factory testing. Recommended to connect to ground for normal operation. TMS K5 I JTAG test mode select. TRST J5 I JTAG test reset. Must be connected to ground if not used TXENABLE K6 I Transmit enable active high input. Internal pull-down. To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS TXENABLE pin to high. To disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. VDDA1 F11, J11 I Analog 1 V supply voltage. VDDA18 G11, H11 I Analog 1.8 V supply voltage. (1.8 V) VDDPLL1 D8, E8 I Analog 1 V supply for PLL. VDDAPLL18 B9, B10 I PLL analog supply voltage. (1.8 V) VDDAVCO18 D9, E9 I Analog supply voltage for VCO (1.8 V) VDDCLK1 G9, H9 I Internal clock buffer supply voltage (1 V). It is recommended to isolate this supply from VDDDIG1 and VDDA1. VDDL1_1 G8, H8 I DAC core supply voltage. (1 V) VDDL2_1 G10, H10 I DAC core supply voltage. (1 V) VDDDIG1 A5, B5, C5, D5, D7, E3, E4, E5, E6, F4, F5, G4, G5 I Digital supply voltage. (1 V). It is recommended to isolate this supply from VDDCLK1 and VDDA1. VDDE1 F7, H7, G6, J6 I Digital Encoder supply voltage (1 V). Must be separated from VDDDIG1 supply VDDIO18 H5 I Supply voltage for all digital I/O and CMOS I/O. VDDOUT18 G12, H12 I DAC output supply. (1.8 V) VDDR18 H2, J2 I Supply voltage for SerDes. (1.8 V) VDDS18 B3, B4 I Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V) VDDT1 H3, J3 I Supply voltage for SerDes termination. (1 V) VDDTX1 B6 I Supply voltage for divided clock output. (1 V) VDDTX18 B7 I Supply voltage for divided clock output . (1.8 V) VEE18N D10, E10, K10, L10 I Analog supply voltage. (-1.8 V) VOUT1+ L12 O DAC channel 1 output. VOUT1- K12 O DAC channel 1 complementary output. VOUT2+ D12 O DAC channel 2 output. Leave pin floating in DAC38RF85 VOUT2- E12 O DAC channel 2 complementary output. Leave pin floating in DAC38RF85 VSENSE D4 O Test pin for on chip parametrics. Can be left floating. VSSCLK A8, A11, B8, B11, B12, F8, F9, F10, J8, J9, J10 - Clock ground. |
同様の部品番号 - DAC38RFxx |
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同様の説明 - DAC38RFxx |
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