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データシートサーチシステム |
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データシートサーチシステム |
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FM30C256 データシート(PDF) 3 Page - List of Unclassifed Manufacturers |
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FM30C256 データシート(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 18 page  FM30C256 Rev 2.1 Dec. 2002 Page 3 of 18 Overview The FM30C256 data collector combines a 256Kb serial nonvolatile RAM with a real-time clock (RTC), a power monitor, and a tamper detect circuit. The FM30C256 integrates these complementary but distinct functions under a common interface in a single package. Despite providing multiple interface Ids as explained below, the product is a single monolithic device. The memory is organized as 32Kx8 of FRAM and is accessed via a separate 2-wire device ID from the remaining functions. This allows the user to preserve addressing information when switching between memory and RTC functions. Modularity in software design is preserved as well. The real-time clock function and the tamper detection is accessed under its own 2-wire device ID. This allows clock data to be read while maintaining the last (most recently used) memory address in the other device. The clock and tamper functions are controlled by 9 registers that are backed up by the external battery. Clock and tamper functions continue to operate from battery power when VDD drops below the battery voltage. In addition to the software-controlled functions, the FM30C256 also provides reset signal for an external microcontroller host. This signal is asserted when VDD drops below the specified trip point (VTP). It remains asserted until VDD returns above VTP for the hold-off period (tRPU). The power monitor has no interaction with other software-controlled functions. Any access to the device will be ignored when VDD < VTP. Memory Operation When accessing the FM30C256, the user addresses 32,768 locations each with 8 data bits. These data bits are shifted in and out serially. The 32,768 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish from other non-memory devices), and an extended 16-bit address. The decoder uses only the lower 15 bits for accessing the memory. The upper address bit should be set to 0 for compatibility with larger devices in the future. The memory is read or written at the speed of the two-wire bus. The interface protocol is described further below. RTC Register Map The interface to clock and tamper functions is via 9 address locations mapped to a separate 2-wire device ID. The interface protocol is described below. The registers contain timekeeping data, control bits, or information flags. A short description of each register follows. Detailed descriptions follow the register summary section. Register Map Summary Table Data Address D7 D6 D5 D4 D3 D2 D1 D0 Function Range 9-F 8 10 years years Years 00-99 7 0 0 0 10 mo months Month 1-12 6 00 10 date date Date 1-31 5 0 000 0 day Day 1-7 4 00 10 hours hours Hours 0-23 3 0 10 minutes minutes Minutes 0-59 2 0 10 seconds seconds Seconds 0-59 1 /OSCEN TSEN CALS CAL4 CAL3 CAL2 CAL1 CAL0 CAL/Control 0 Tamper CF reserved reserved TST CAL W R Flags/Control ILLEGAL ADDRESSES |
同様の部品番号 - FM30C256 |
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同様の説明 - FM30C256 |
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