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MC14XXXBCL データシート(PDF) 3 Page - Motorola, Inc

部品番号 MC14XXXBCL
部品情報  Dual 4?밒nput ?쏯AND??Gate 2?밒nput ?쏯OR/OR??Gate 8?밒nput ?쏛ND/NAND??Gate
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メーカー  MOTOROLA [Motorola, Inc]
ホームページ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC14XXXBCL データシート(HTML) 3 Page - Motorola, Inc

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MOTOROLA CMOS LOGIC DATA
3
MC14501UB
SWITCHING CHARACTERISTICS** (CL = 50 pF, TA = 25_C)
Characteristic
Figure
Symbol
VDD
Typ #
Max
Unit
Output Rise Time
NAND, NOR
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
2, 3
tTLH
5.0
10
15
180
90
65
360
180
130
ns
Output Fall Time
NAND, NOR
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
2, 3
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Output Rise Time
NOR–Inverter
tTLH = (1.35 ns/pF) CL + 32.5 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/pF) CL + 17 ns
3
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
NOR–Inverter
tTHL = (0.67 ns/pF) CL + 26.5 ns
tTHL = (0.45 ns/pF) CL + 17.5 ns
tTHL = (0.37 ns/pF) CL + 11.5 ns
3
tTHL
5.0
10
15
60
40
30
120
80
60
ns
Propagation Delay Time
NAND
tPLH, tPHL = (1.7 ns/pF) CL + 45 ns
tPLH, tPHL = (0.66 ns/pF) CL + 37 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
2
tPLH,
tPHL
50
10
15
130
70
50
260
140
100
ns
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns
NOR
tPLH, tPHL = (0.66 ns/pF) CL + 32 ns
tPLH, tPHL = (0.5 ns/pF) CL + 20 ns
3
tPLH
tPHL
5.0
10
15
115
65
45
230
130
90
ns
tPLH, tPHL = (1.7 ns/pF) CL + 45 ns
NOR–Inverter
tPLH, tPHL = (0.66 ns/pF) CL + 37 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
3
tPLH,
tPHL
5.0
10
15
130
70
50
260
140
100
ns
* The formulas given are for the typical characteristics only at 25
_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.


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