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Si50122-A3-GMR データシート(PDF) 5 Page - Silicon Laboratories |
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Si50122-A3-GMR データシート(HTML) 5 Page - Silicon Laboratories |
5 / 14 page Si50122-A3/A4 Rev 0.7 5 Table 3. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit DIFF Clocks Duty Cycle TDC Measured at 0 V differential 45 — 55 % Skew TSKEW Measured at 0 V differential — — 100 ps Output Frequency FOUT VDD = 3.3 V — 100 — MHz Frequency Accuracy FACC All output clocks — — 100 ppm Slew Rate tr/f2 Measured differentially from ±150 mV 0.6 — 5.0 V/ns Crossing Point Voltage at 0.7 V Swing VOX 300 — 550 mV Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V Spread Range SRNG Down Spread, –A4 only — — –0.5 % Modulation Frequency FMOD –A4 only 30 31.5 33 kHz DIFF Clocks Jitter Parameters, VDD = 3.3 V ± 10% PCIe Gen1 Pk-Pk Pk-PkGEN1 PCIe Gen 1 — 20.7 35 ps PCIe Gen2 Phase Jitter RMSGEN2 10 kHZ < F < 1.5 MHz —0.8 2.1 ps 1.5 MHZ < F < Nyquist —1.4 2.2 ps DIFF Clocks Jitter Parameters, VDD = 2.5V ± 10% PCIe Gen1 Pk-Pk Pk-PkGEN1 PCIe Gen 1 —25 40 ps PCIe Gen2 Phase Jitter RMSGEN2 10 kHZ < F < 1.5 MHz —0.9 2.9 ps 1.5 MHZ < F < Nyquist —1.7 3.0 ps 25 MHz at 3.3 V Duty Cycle TDC Measurement at 1.5 V 45 — 55 % Output Rise Time tr CL = 10 pF, 20% to 80% 1.2 3.0 ns Output Fall Time tf CL = 10 pF, 20% to 80% 1.2 3.0 ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 250 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm Powerup Time Clock Stabilization from Powerup TSTABLE First powerup to first output — — 10 ms Note: Visit www.pcisig.com for complete PCIe specifications. |
同様の部品番号 - Si50122-A3-GMR |
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同様の説明 - Si50122-A3-GMR |
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