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データシートサーチシステム |
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データシートサーチシステム |
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ISL29501 データシート(PDF) 6 Page - Intersil Corporation |
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ISL29501 データシート(HTML) 6 Page - Intersil Corporation |
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6 / 23 page  ISL29501 6 FN8681.3 June 29, 2016 Submit Document Feedback I2C Electrical Specifications For SCL, SDA, A1, A2, IRQ Unless otherwise stated, VDD = 3V, TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP (Note 9) MAX (Note 8)UNIT Supply Voltage Range for I2C Specification VI2C 1.8 3.3 V Input Leakage IIL VIN = GND to VCC 1 µA Input LOW Voltage VIL -0.3 0.3 x VCC V Input HIGH Voltage VIH 0.7 x VCC VCC + 0.3 V SDA and SCL Input Buffer Hysteresis Vhys 0.05 x VCC V SDA Output Buffer low Voltage VOL IOL = 3mA 00.4 V Pin Capacitance (Note 10)Cpin 10 pF SCL Frequency fSCL 400 kHz Pulse Width Suppression Time At SDA and SCL Inputs tsp Any pulse narrower than the maximum specification is suppressed 50 ns SCL Falling Edge to SDA Output Data Valid tAA SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window 900 ns Time the Bus Must Be Free Before the Start of A New Transmission tBUF SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition 1300 ns Clock Low Time tLOW Measured at the 30% of VCC crossing 1300 ns Clock High Time tHIGH Measured at the 70% of VCC crossing 600 ns START Condition Set-Up Time tSU:STA SCL rising edge to SDA falling edge; both crossing 70% of VCC 600 ns START Condition Hold Time tHD:STA From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC 600 ns Input Data Set-Up Time tSU:DAT From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns Input Data Hold Time tHD:DAT From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 0 ns STOP Condition Set-Up Time tSU:STO From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC 600 ns STOP Condition Hold Time for Read, or Volatile Only Write tHD:STO From SDA rising edge to SCL falling edge; both crossing 70% of VCC 1300 ns Output Data Hold Time tDH From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0 ns SDA and SCL Rise Time tR From 30% to 70% of VCC 20 + 0.1 x cb 250 ns SDA and SCL Fall Time tF From 70% to 30% of VCC 20 + 0.1 x cb 250 ns Capacitive Loading of SDA or SCL Cb Total on-chip and off-chip 10 400 pF SDA and SCL Bus Pull-Up Resistor Off-Chip Rpu Maximum is determined by tR and tF For Cb = 400pF, maximum is about 2kΩ ~2.5kΩ For Cb = 40pF, maximum is about 15kΩ ~ 20kΩ 1 kΩ Output Leakage Current (SDA only) ILO VOUT = GND to VCC 1 µA A1, A2, SDA and SCL Input Buffer low Voltage VIL -0.3 VCC x 0.3 V |
同様の部品番号 - ISL29501 |
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同様の説明 - ISL29501 |
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